A desire to listen to music late at night, and a hi-fi amplifier with no headphone output, prompted the design of the Headphone
Amplifier circuit shown in Fig.2. It is intended to deliver 100mW into 32 ohms when driven by line-level signals (1V peak); this
allows musical peaks, and dips in the headphone impedance, to be handled without clipping, but most headphones will produce
adequate volume levels with a few milliwatts. The circuit diagram shows a single audio channel, components marked with an
asterisk (*) are duplicated for the second channel.

A desire to listen to music late at night, and a hi-fi amplifier with no headphone output, prompted the design of the Headphone Amplifier circuit shown in Fig.2. It is intended to deliver 100mW into 32 ohms when driven by line-level signals (1V peak); this allows musical peaks, and dips in the headphone impedance, to be handled without clipping, but most headphones will produce adequate volume levels with a few milliwatts. The circuit diagram shows a single audio channel, components marked with an asterisk (*) are duplicated for the second channel.

The power amplifier is of a conventional design, with voltage gain given by (1 + R6/ R7). IC3 is a dual NE5532 op.amp with excellent noise and distortion performance, but it cannot drive headphones directly, so a discrete output stage built around transistors TR2 and TR3 is added. Current source TR1, resistors R8 toR10, and diodes D6, D7 provide stable biasing for the output transistors. These do not require heatsinks, and the presence of diodes D6 and D7 minimises the effect of ambient temperature on the quiescent current.

A pushbutton volume control system is implemented using IC2, which is a DS1666- 10 digital potentiometer (available from RS Components) that simulates a single-gang log. law 10k pot. The DS1666 was chosen because it has a simple control interface, and also because it has a VBIAS pin (12) that can be held at a negative voltage so that analogue signals of either polarity can be controlled.

The chip’s “wiper” (VW) can be “moved” between the VH and VL terminals (pins 10 and 9). The CS input pin 4 must be held low in order to vary the setting. Then, a pulse at the INC input (pin 3) moves VW by one step: towards VH if the U/ D input pin 2 is high, and towards VL if U/ D is low. An oscillator based on Schmitt trigger IC1b provides the clock pulses.When one of the non-latching switches S1 or S2 are closed, the CS input is pulled low after a debouncing delay determined by R4and C2, the U/ D input is held at the appropriate logical level by D3 and/or R3, and clock pulses are gated to the INC pin via ICla,to increase or decrease the volume.

To avoid the bulk and stray fields of a transformer in the enclosure, the amplifier was powered by a separate plug-in 12V mains adapter. Designing with op.amps is simpler with symmetrical supplies, so after pre-regulation by TR4, a negative rail was generated by two ICL7660SCPA d.c.-d.c. converters IC4 and IC5 connected in parallel to reduce output impedance, with final regulation provided by a couple of three-terminal regulators, IC6 and IC7. Light-emitting diode D10 provides a power-on indication.

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