The terms positive logic and negative logic refer to two conventions that dictate the relationship between logical values and the physical voltages used to represent them. Unfortunately, although the core concepts are relatively simple, fully comprehending all of the implications associated with these conventions requires an exercise in lateral thinking sufficient to make even a strong man break down and weep!

Before plunging into the fray, it is important to understand that logic 0 and logic 1 are always equivalent to FALSE and TRUE, respectively (unless you’re really taking a walk on the wild side, in which case all bets are off). The reason these terms are used interchangeably is that digital functions can be considered to represent either logical or arithmetic operations (Figure 1).

Figure 1. Logical versus arithmetic views of a digital function.

Having said this, it is generally preferable to employ a single consistent format to cover both cases, and it's easier to view logical operations in terms of 0s and 1s than it is to view arithmetic operations in terms of Fs and Ts. The key point to remember as we go forward is that, by definition, logic 0 and logic 1 are logical concepts that have no direct relationship to any physical values.

Physical to Logical Mapping (NMOS Logic)
Let’s gird up our loins and meander our way through the morass one step at a time... The process of relating logical values to physical voltages begins by defining the frames of reference to be used. One absolute frame of reference is provided by truth tables, which are always associated with specific functions (Figure 2).

Figure 2. Absolute relationships between logical functions and their truth tables.

Another absolute frame of reference is found in the physical world, where specific voltage levels applied to the inputs of a digital function cause corresponding voltage responses on the outputs. These relationships can also be represented in truth table form. Consider a logic gate constructed using only NMOS transistors (Figure 3).

Figure 3. The physical mapping of an NMOS logic gate.

With NMOS transistors connected as shown in Figure 3, an input connected to the more negative V_SS, turns that transistor OFF, and an input connected to the more positive V_DD turns that transistor ON. The final step is to define the mapping between the physical and logical worlds; either 0V is mapped to FALSE and +ve (the more positive supply rail) is mapped to TRUE, or vice versa (Figure 4).

Figure 4. The physical-to-logical mapping of our NMOS logic gate.

Using the positive logic convention, the more positive potential is considered to represent TRUE and the more negative potential is considered to represent FALSE (hence, positive logic is also known as positive-true). By comparison, using the negative logic convention, the more negative potential is considered to represent TRUE and the more positive potential is considered to represent FALSE (hence, negative logic is also known as negative-true.). Thus, this circuit may be considered to be performing either a NAND function in positive logic or a NOR function in negative logic. (Are we having fun yet?)

Physical to Logical Mapping (PMOS Logic)
From the previous example it would appear that positive logic is the more intuitive as it is easy to relate logic 0 to 0V (no volts) and logic 1 to +ve (presence of volts). On this basis, one may wonder why negative logic ever reared its ugly head. The answer to this is, as are so many things, rooted in history.

When the MOSFET technology was originally developed, PMOS transistors were easier to manufacture and were more reliable than their NMOS counterparts (in the very early days, PMOS transistors were the only ones that worked at all; due to a variety of problems, the first NMOS transistors were permanently ON, which wasn't much use to anyone). Thus, the majority of early MOSFET-based logic gates were constructed from combinations of PMOS transistors and resistors. Consider a logic gate constructed using only PMOS transistors (Figure 5).

Figure 5. The physical mapping of a PMOS gate.

Circuits constructed using the original PMOS transistors typically made use of a negative power supply; that is, a power supply with a 0V rail and a negative (–ve) rail. With PMOS transistors connected as shown in Figure 5, an input connected to the more positive 0V rail turns that transistor OFF, while an input connected to the more negative –ve rail turns that transistor ON. Once again, the final step is to define the mapping between the physical and logical worlds; either 0V is mapped to FALSE and –ve is mapped to TRUE, or vice versa (Figure 6).

Figure 6. The physical-to-logical mapping of our PMOS logic gate.

Thus, this circuit may be considered to be performing either a NOR function in positive logic or a NAND function in negative logic. In this case, negative logic is the more intuitive as it is easy to relate logic 0 to 0V (no volts) and logic 1 to –ve (presence of volts). Additionally, the physical structure of the PMOS gate is identical to that of the NMOS gate; if the NMOS gate is represented in positive logic and the PMOS gate is represented in negative logic, then both representations equate to NAND functions, which is, if nothing else, aesthetically pleasing.

Note: See also my articles on Reed Müller Logic and Assertion-Level Logic.