Ken Coffman's ever-popular Verilog Cheatsheet

I'll send you a printed copy (which, believe me, fits on one sheet of paper) if you contact me.

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General note: Verilog is a case-sensitive language and all keywords are lower-case.

Data types include single bits, bit vectors (bus [31:0]), integers (32 bit values), and strings “string value”.

Number Formats

Decimal is the default format.

decimal    3`599

`h             hex          16`h6abf

`b             binary      4`b0001

`o             octal         2`o77

Bit Values

1, 0, X (unknown), and Z (high impedance.

Signal Types include wires and regs. A wire (simply a net) can have multiple drivers. A reg is a memory element which can represent a latch output (created by combinational logic), a flipflop output, or memory cell output. The signal type will be inferred from the code.

Verilog Operators (Bitwise)

|               OR

&             AND

~              Inversion

^              XOR

~&           NAND

 ~|            NOR

 ~^           XNOR

Verilog Operators (Logical)

!               Inversion

&&          Are values both true? Returns true/false

==            Are values logically equal? Returns true/false.

===          Are values identical (includes X and Z)? Returns true/false.

Language Elements

//              Comment identifier

=              Blocking assignment Note: Use assignment only for combinational logic.

<=            Non-blocking assignment. Note: Use non-blocking for all synchronous assignment.

begin/end Required for multi-assignment code sections.

Concatenation is identified with curly brackets {,}for example:

 {bus[16:8], 4`b0, 4`hz}

NOR Gate Example

module nor_gate (in1, in2, out1);

input        in1, in2;

output     out1;

always     out1 = in1 ~| in2;

endmodule

Flipflop Example

module edgetrig (clk, rst, test_in1, enable_input, test_out2);

input        clk, rst, test_in1, enable_input;

output     test_out2;

reg           test_out1, test_out2;

always @ (posedge clk) begin

if (rst) test_out1       <= 1`b0;

else if (enable_input) begin

test_out2  <= test_out1;

test_out1  <= test_in1;

end end

endmodule

Port Assignments

Port assignments can be positional (where the calling module ordered list exactly matches the underlying module port list signal by signal and all signals must be connected) or by name.

Ordered list example:

Testmodule u1 (in1,in2,out1);

Named List

The format for by name assignment is: (.in1(sig1),.in2(sig2),.out1(sig3);

Where sig1/sig2/sig3 represent names in the calling module and in1/in2/out1 represent names in the underlying module port list. In a named list, the ports can appear in any order and underlying signals can be unused by leaving the connection undefined like in2 here: (.in1(sig1),.in2(),.out1(sig3);

Conditionals include:

if, else if, else

See the state machine for an example of usage.

Case Format

Note: define all input combinations or an unwanted latch will be created.

always @ (select value) begin

                default assignment;

case (select value)

                value1:     assignment;

                value2:     assignment;

                valuen:     assignment;

endcase

end

Tristate Code Example

module tristate (input_bus, output_bus, tri_control);

input        [7:0]        input_bus;

input                        tri_control;

                // Tristate control signal.

output [7:0] output_bus;

// The first condition is

//  the tri_control true

//  condition, the second is

//  the false condition.

assign output_bus = tri_control ? input_bus : 8'bz;

endmodule

Bidirectional Code Example

module bidir (bidir_bus, direction_sig, use_bidir_sig);

inout        [7:0]        bidir_bus;

input                        direction_sig;

output     [7:0]        use_bidir_sig;

reg           [7:0]        output_bus;

wire         [7:0]        bidir_input;

// When direction_sig is true,

// output_bus drives the bidir_bus

//  port pins.

// The bidir_bus signals are

//  accessible inside the design

//  on the bidir_input bus.

// Output part, MUX form.

assign bidir_bus = direction_sig ? output_bus : 8'bz;

// Input part.

assign bidir_input    =  bidir_bus;

assign use_bidir_sig                =  bidir_input;

endmodule

State Machine Example

module gray1 (clk, reset, cnt, flag_output);

input                        clk, reset;

output                     cnt;

wire         [2:0]        cnt; // cnt is

// the present-state logic.

reg           [2:0]        next_state;

output                     flag_output;

reg                           flag_output;

assign cnt = next_state;

always @ (posedge clk or posedge reset)

if (reset)   begin

next_state                  <= 3'b0;

flag_output  <= 1'b0;

                end

else begin case (next_state)

3'b000:    begin

next_state   <= 3'b001;

flag_output <= 1'b0;

end

3'b001:    begin

next_state                <= 3'b011;

flag_output <= 1'b0;

                end

3'b011:    begin

next_state                <=  3'b010;

flag_output <= 1'b1;

                end

3'b010:    begin

next_state                  <= 3'b110;

flag_output  <= 1'b0;

                end

3'b110:    begin

next_state                  <= 3'b111;

flag_output  <= 1'b0;

                end

3'b111:    begin

next_state                  <= 3'b101;

flag_output  <= 1'b0;

                end

3'b101:    begin

next_state                  <=  3'b100;

flag_output  <=  1'b0;

                end

3'b100:    begin

next_state                <= 3'b000;

flag_output <= 1'b0;

                end

            default:   begin

next_state                <= 3'b0;

flag_output <= 1'b0;

end endcase end

endmodule

These code examples are from Ken Coffman’s Real World FPGA Design with Verilog which is available from: amazon.com