Industry's First Serial RapidIO 2.1 IP Solution

Written by Clive Maxfield November 16, 2009 Hits: 399 Favorites

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I just heard from the folks at Altera that they have just launched the industry’s first IP core supporting the Serial RapidIO 2.1 specification.

Altera's Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane. Used in conjunction with Altera’s Stratix IV FPGAs, the IP core enables 20 GBaud performance in applications ranging from wireless basestations, high-performance military systems and DSP farms. The IP core is optimized for Stratix IV FPGAs with embedded transceivers and is supported within Quartus II software v9.1.

Altera

The RapidIO 2.1 specification enables increased performance up to 20 GBaud in applications ranging from next-generation wireless basestations, high-performance military systems and DSP farms. Support for the RapidIO 2.1 specification builds upon Altera's complete Serial RapidIO solution, which includes an end-point IP core that is backward compatible to the RapidIO 1.3 specification, reference designs, application notes, testbenches, and interoperability reports with leading digital signal processor and switch vendors.

The Serial RapidIO IP core has been qualified against the RapidIO Trade Association's bus functional model and is supported within Altera's 40-nm Stratix IV GX and Stratix IV GT FPGAs and HardCopy IV GX ASICs.

Pricing and Availability
The Serial RapidIO IP solution is part of Altera's MegaCoreIP Library and is available now for evaluation upon download and installation of Quartus II software v9.1. To download the combined Quartus II software and MegaCore IP library, visit the Download Center. Licensing and pricing information for the Serial RapidIO IP core is available by contacting your local Altera sales representative. Additional information on Altera's Serial RapidIO solutions can be found at the RapidIO MegaCore Function page.

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Written by :

Clive Maxfield