As we all know, it's not the size of your silicon chip, it's what you do with it (grin). Having said that, it's hard to resist the lure of "bigger and better", so I was interested to see that the theme of Magma's Winter 2009 issue of their MagmaWire newsletter is "Big Chips"

Just in case you haven’t signed up for this newsletter, I post an abstract of it here (below) with Magma's kind permission (Click Here to see the full version).

In this MagmaWire we look at the push toward designing bigger chips. Remember when the prospect of a 10-million gate design was a big deal? That is so yesterday. Today designers are targeting 40-million-gate designs, looking toward designs of 100-million gates, and some SoC designers’ roadmaps point toward 1 billion gates. The challenges are many, and we know leading-edge design is both costly and resource intensive. Magma CEO Rajeev Madhavan offers his perspective on these challenges.

Also included are the following articles that provide more information about the latest features in Magma products that enable the design of large chips:

• Better Floorplans for the Biggest Designs
• Synthesize Larger Designs Faster
• More Timing Analysis is Not the Answer at 28 nm
• Integrated Physical Verification Lowers Cost of Design

Better Floorplans for the Biggest Designs
The traditional, predominately interactive approach to chip planning and design feasibility analysis has become too time consuming and inaccurate for large systems on a chip. Hydra, Magma’s hierarchical design planning solution, provides designers the ideal combination of advanced capabilities and broad flexibility, letting them apply their expertise to critical issues while automating significant portions of the flow.

Recently announced enhancements in Hydra 1.1 give the macro placer improved capacity with support for thousands of macros, improved congestion and timing awareness for both inter-block and intra-block communication, and extended relative placement constraint support.

The shaper now supports any mix of design styles including channel style, near abutment and full abutment. The slack-proportionate time budgeting and incremental re-budgeting capabilities deliver more accurate budgets than traditional methods. Hydra 1.1's new clock planning technology supports both top-down and bottom-up clock tree construction. With native support for hierarchy and multi-threading, Hydra 1.1’s timing-driven global router constructs the signal topologies required for pin assignments and accurate congestion analysis during the chip planning stage.

Read the recent ESNUG posting where Open-Silicon describes how they saved 12 to 14 man-weeks using Hydra.

To learn more about how Hydra delivers better floorplans and faster results for the biggest designs, download the Got Design Planning? white paper

Synthesize Larger Designs Faster
Design teams are facing increasing pressure to build larger, more complex chips with fewer resources and shorter delivery schedules. Talus Design and Talus RTL are fast, high-capacity synthesis solutions that optimize for power, area and timing, and generate both gate-level netlists and Magma Volcano databases for handoff. Talus RTL provides a complete RTL-to-netlist synthesis solution while Talus Design adds physical synthesis capabilities to deliver higher levels of predictability and performance. Unlike traditional synthesis tools, a single Talus Design or Talus RTL license provides a comprehensive synthesis solution with seamless scan insertion and scan optimization that supports VHDL, Verilog and System Verilog.

New RTL-to-GDSII reference flows for leading IP providers including ARM, MIPS and Imagination Technologies are available in version 1.1 of Talus Design and Talus RTL. The reference flows and enhancements make it easier to get better results out of the box.

For more details on recent upgrades, get the new Talus Design and Talus RTL data sheets.

More Timing Analysis is Not the Answer at 28 nm
At the 28-nanometer node designs are expected to exceed 100 million gates, have 15 or more process, voltage and temperature (PVT) corners, supply voltages under 1V and shorter design cycles. To handle the size and complexity of these ICs, design teams must reevaluate every aspect of their design methodology, including resource planning, design architecture and final timing sign-off solutions. In this article recently featured in Chip Design, Magma’s Bob Smith outlines the limitations of conventional static timing analysis (STA) tools and what the next generation of STA tools will need to have to meet designers’ needs for higher capacity, greater accuracy and faster turnaround time. Read more.

Integrated Physical Verification Lowers the Cost of Designs at 65/40 nm and Below
Meeting manufacturing requirements at 65 nm and below requires running sign-off physical verification (DRC/LVS) concurrently with place and route. Magma has pioneered this capability with Talus qDRC and Talus qLVS, which integrate the sign-off Quartz physical verification products into Talus.

Integrating physical verification into the RTL-to-GDSII flow allows users to avoid costly last-minute iterations between GDS-based DRC/LVS tools and Talus, decreasing project cycles by weeks. Talus users are also able to improve timing convergence and better manage power by using Talus qDRC’s timing-driven pattern-based fill capability. Because Talus qDRC and Talus qLVS are based on the popular sign-off Quartz DRC and Quartz LVS products, they provide full sign-off capabilities with turnaround times up to 10x faster than legacy tools.

Learn more, download the Moving Sign-off into the Implementation Flow with Talus qDRC white paper