Please help me if you can, Xilinx FIFO Issue!

Written by Antti Lukats December 21, 2009 Hits: 521 Favorites

5.0 (1)

I hope my plea will not be seen as usual "please help me" request. I
do my (home)work, I try hard but sometimes there come up problems that
seem very hard to solve, with the current problem, well if there is no
solution to that, then I wonder how come it has been ever been
possible to use Xilinx FIFO's with problem at all? So the problem:

Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY
flags present.

signals at input correct, as expected (checked with ChipScope)
signals at output:
- double value
- missing 1, 2 or 3 values
- FIFO will read out random number of OLD entries, this could be 4
values, or 50% of the FIFO old values

I can select BRAM or FIFO16 implementation in Coregen, it doesnt
change the problem

Virtex-4, ISE 10.1SP3

Please help me, if anyone has some good suggestion (except use Altera
advice), I am getting really desperate. To the extent that when i
friend called my yesterday, then after my "hello", his first response
was: "Are you dead?". I had to explain that i am not.

User reviews

Average user rating from: 1 user(s)

To write a review please register or login.

Overall:

5.0

A Few Comments

Overall:

5.0

Reviewed by Ken Coffman
December 21, 2009

Comments (2)
Report this review

FIFOs are always tricky, particularly the asynchronous ones. I believe the Xilinx Async FIFO-16 can only hold 15 values, did you know that?

It might help to understand how they work (and I apologize if you already know all this). The FIFO memory is a block of RAM (either a RAM block or distributed RAM). There are separate read and write counters which point to the different locations (and roll over after terminal count). It's much better to use almost full and almost empty flags to meter the data flow with a little more margin.
Good luck Antti and let us know when you nail the solution.

Written by :

Antti Lukats