Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the second question: "What are the main benefits that users are deriving from SystemC and TLM?"

Question #2: What are the main benefits that users are deriving from SystemC and TLM?

How a TLM-driven flow improves productivity

Steve Brown (Cadence): Most SystemC usage today is for reference models for simulation, evaluating architectural tradeoffs, and for supporting software development. Increasingly, customers are exploring the high level synthesis of SystemC and functional verification of the TLM – increasing the number of ways of investing in SystemC results in fewer bugs, shorter verification schedules, and higher productivity creating RTL code. We see customers with nearly 10x fewer lines of SystemC than RTL for design, 10x faster simulation speed for functional verification, and week's earlier jump on hardware/software co-verification.

Andreas Ropers (ARM): In the past, developers of virtual platforms had to deal with multiple proprietary interfaces, making it costly to create a single platform of components from different sources. Using SystemC and TLM-2.0, we are now in a position where customers can rely on a common simulation interface and communication mechanism between models. There is a high likelihood that models from different vendors will work with each other. Designer can use the simulation environment of their choice. Furthermore this offers a great flexibility since the same IP model can be used for different tasks in the most suitable environment.

Patrick Sheridan (CoWare): You can think of a virtual platform as the virtualized representation of an electronic system, where the focus is on designing the system right the first time. The benefits of electronic system virtualization include better products, reduced development schedules and costs, and improved collaboration in the design chain. For example, CoWare virtual platforms are used in production today for product planning (to increase collaboration between semiconductor companies and OEMs on design tradeoffs and reduce risk), for concurrent system development (enabling architecture, software, and hardware teams to work more in parallel, with earlier and more continuous points of system integration that increases quality and reduces schedule), and post-silicon (where the superior system-level visibility provided by virtual platforms continues to provide benefits for software development, documentation development, manufacturing test development, and customer support).

Frans Theeuwen (NXP): The main benefits are the reduction in time-to-market and the improvement of the quality of the created designs. The reduced time-to-market is obtained because the SystemC models provide software developers a platform for developing and debugging their driver software and application software before the actual silicon becomes available. Quality improvement is reached through the ability to perform architectural exploration and feasibility studies early in the design process. As such, better "tuned" architectures can be created.

Shabtay Matalon (Mentor): SystemC offers an abstracted view that enable designers to conceptualize complex systems. The benefits provided to the users are:

• Comprehending and validating system requirements before building the RTL
• Optimizing the architecture to meet performance and power requirements
• Creating a virtual prototype for validating and debugging software against the hardware even before RTL is built.
• Reducing the RTL verification effort significantly by catching bugs earlier and faster
• Reducing the RTL verification effort by reusing ESL components in RTL testbench

Laurent Ducousso (STMicroelectronics): A C/C++ simulator kernel to manage concurrency; an efficient way to capture an early abstracted view of the design; a reference model at the IP level; a software development platform; and architecture exploration.

Simon Davidmann (Imperas): Users of Virtual Platforms are seeing benefits of reduced software development schedules and higher quality software being produced. As software gets more complex, simulation – as provided by SystemC/TLM-2.0 environments – becomes much more important.

Nagendra Gulur Dwarakanath (TI): Predominantly, we use simulators to help explore device architectures and to deliver software early to our customers. Distributed IP model development and interoperability are extremely important to achieve these use-cases. SystemC and TLM are key enablers.

Marc Schmitz (STEricsson): SystemC enables users to raise the level of abstraction and thus to model systems that get more and more complex in order to meet the current needs required by the design process.

Ravi Venugopalan (Sonics): The main benefits are early architectural exploration. Also, verification of the system and sub-system blocks can commence even before a single line of RTL is available.

David Beal (Virtutech): SystemC provides a semi-standardized means by which disparate models provided by different organizations can provide a certain level of interoperability. This better ensures IP re-use and it allows modeling skills created in one part of the organization to be applied to other parts of the organization.

J.C. Yeh (ITRI): Rapid system-level simulation and hardware/software co-simulation.

Brian Bailey (Independent Consultant): The primary philosophy behind the creation of SystemC was to take the most widely used language (C,C++) and to add necessary hardware concepts. The language foundation means that most people are familiar with its programming concepts, and timing, concurrency and hierarchical structure have been added. It also adds the flexibility and modularity that comes from the C++ language – which goes beyond anything offered by other hardware description languages.

Question #1 | Introduction/Overview | Question #3