Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the third question: "How does SystemC adoption help address the critical path of today's systems projects?"

Question #3: How does SystemC adoption help address the critical path of today's systems projects?

Motivations for TLM - Addressing System Project Critical Path

Andreas Ropers (ARM): Using virtual prototypes means that software developers can start the development well ahead of silicon availability.

Patrick Sheridan (CoWare): SystemC and TLM industry standards are the native language of choice for the creation of virtual platforms and component IP models. The ability of SystemC to support multiple levels of TLM abstraction enables virtual platforms to be described at the right level of detail for the design task. For example, model developers creating a model for software development can save time and increase simulation speed by avoiding detail in the model that isn't necessary to run the software. Alternatively, multiple levels of abstraction can be mixed together in a SystemC TLM platform when required by the design task, such as system verification, where transactors and HDL co-simulation are used to connect the platform to the RTL subsystem DUT. Finally, the strong industry alignment on SystemC TLM-2.0 standards for model interoperability is increasing model supply, increasing model reuse, and improving the industry ROI for model development.

Frans Theeuwen (NXP): As I mentioned before, SystemC virtual prototype environments enable software designers to develop and debug their software in parallel with the hardware design. We have seen in a number of design projects that this can result in a time-to-market reduction of 8 to 12 weeks.

Shabtay Matalon (Mentor): SystemC, which is derived from C/C++, provides a unified level of abstraction for hardware, software, and data objects. This unification allows sharing development and infrastructure resources, thereby reducing the costs of embedded system and SoC designs. Specifically, it shortens project design schedule by addressing the following critical design tasks:

• Comprehending and validating system requirements before building the RTL
• Optimizing the architecture to meet performance and power requirements
• Creating a virtual prototype for validating and debugging software against the hardware way before RTL is built.
• Reducing the RTL verification effort significantly by catching bugs earlier and faster
• Reducing the RTL verification effort by reusing ESL components in RTL testbench

Laurent Ducousso (STMicroelectronics): Early firmware and software development; validation of architecture concepts; providing a reference for verification, and horizontal and vertical reuse inside and across projects.

Simon Davidmann (Imperas): Today, more often than not, software is the critical path for systems projects. Project managers view hardware problems as well understood, if not solved. The value-add for systems/products – and the differentiation – is embodied in the software, not the hardware. So tools and methodology that can improve software development productivity and quality, as SystemC/TLM-2.0 does, are directly helping the successful delivery of systems and products.

Nagendra Gulur Dwarakanath (TI): Early modeling is important to ensure functional and performance verification of chips in a timely manner. Given the increasing complexity of chips and IP, it is important to invest in a scalable approach to model development. A lot of the time, the IP models need to be implemented by the IP experts. For this model of development to become efficient and successful, we need comprehensive standards and supporting tools. SystemC helps address this not only by providing a standard but also by enabling a large eco-system of tool vendors, training houses, and model repositories to be established.

Marc Schmitz (STEricsson): In many ways! For instance, SystemC-based development platforms enable design teams to commence software development a long time before silicon availability, which leads to significantly decrease time-to-market.

Ravi Venugopalan (Sonics): The performance of the system is very important for every system that is being built today. Analyzing the performance early in the project – rather than later – helps early closure on the architecture. SystemC models assist with early architectural exploration as well as provide a path to have an architectural reference model for use in verification. Both of these can be used to reduce the verification time which is the critical path for the hardware design. The architectural reference models also provide an early entry point for the system software operating system and application development.

David Beal (Virtutech): SystemC use for modeling of devices from very early stages of their hardware development means that TLM models remain available during later software and system development stages of the project.

J.C. Yeh (ITRI): SystemC and TLM are very useful with regard to system modeling. By means of a system-level virtual platform, system performance analyses and system architecture exploration can be realized.

Brian Bailey (Independent Consultant): For many companies, the two things on their critical path are verification and software. SystemC helps them out in both cases. For verification, the design model executes orders of magnitude faster than a corresponding RTL model and thus allows for many more and longer runs to be performed than would otherwise be possible. The high simulation speed also makes it possible to execute software much earlier than had been possible in the past.

Steve Brown (Cadence): There are two major items in the critical path: starting software development and verification, and implementation and functional verification of the design. SystemC enables users to build an early model of the hardware that models the register interfaces needed for embedded software development, much earlier than today's RTL, or even emulation. Even FPGA prototyping is later because it requires RTL to be complete to generate the FPGA. SystemC synthesis and functional verification reduces schedules by shortening the time to create the design (versus RTL), enabling earlier functional verification of the TLM (versus RTL), and reducing the heavy functional verification burden and RTL iteration cycles. Customers are exploring ESL architecture tools, but they tell us they need a more productive path to implement the and functionally verify the design in order to impact their project schedules. The other reality we have to deal with is the amount of legacy RTL code, and the implication that any SystemC solution must accommodate mixed SystemC/RTL.

Question #2 | Introduction/Overview | Question #4