Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the fourth question: "Is the adoption of SystemC and TLM being limited or held back in any way?"

Question #4: Is the adoption of SystemC and TLM being limited or held back in any way?

Abstraction Raises Productivity

Patrick Sheridan (CoWare): Primarily this is a management question related to planning and project deployment. The value propositions for using SystemC and TLM for electronic system virtualization are proven, but companies adopting these methodologies for the first time need to create a plan and understand the steps needed to successfully deploy them. You should not jump into a modeling project without clear objectives for the design tasks to be performed and the requirements they place (and don't place) on the virtual platform. With a clear definition of the project goals and the scope of the modeling task, you can clearly set management expectations, ensure that resources are available for creation and use (both staff and production quality tooling), and deliver high value results for the design task.

Frans Theeuwen (NXP): One of the problems with regard to the introduction of SystemC is the new language and the richness of the language. Although this gives the modelers lots of powerful constructs for modeling, it also "invites" the modelers to come up with models that do not interface with each other. TLM and TLM2.0 are good steps in the direction to guide the modelers in the way they should use SystemC.

Shabtay Matalon (Mentor): The largest challenge to adoption of SystemC and TLM is the lack of SystemC TLM 2.0 models. As more IP providers begin to deliver TLM2.0 compatible models, this will become less of an issue.

Laurent Ducousso (STMicroelectronics): Adopting SystemC and TLM for modeling requires software skills, but there is a limited population of people with these skills available in the design community.

Simon Davidmann (Imperas): Models are a big factor, especially high-quality, instruction-accurate models of processors. But equally as important is for the users to see the value of the end implementation.

Nagendra Gulur Dwarakanath (TI): This is an important question. We believe that adoption and growth of these standards is limited by the pace at which the standards can embrace comprehensive model development requirements. To some extent, SystemC has primarily been an "architect's tool". With TLM, it is beginning to address the broad "software simulators/virtual platforms" space. TLM did a great job of raising the abstraction of how we implement bus interfaces, thereby promoting easier construction and higher speed simulations. We need similar standards to come up around the areas of IP configuration, analysis, debug, and non-memory-mapped busses.

Marc Schmitz (STEricsson): I don't think so. It is several years now that the technology is mature and the interoperability issues with other languages have been solved. Moreover, a lot of SystemC components have been developed by third parties and can be used to assemble a platform.

Ravi Venugopalan (Sonics): Limited to Europe and Japan and very little elsewhere.

David Beal (Virtutech): The specifications are incomplete and specify only a portion of the aspects that are necessary to ensure complete interoperability and model standardization.

J.C. Yeh (ITRI): Hardware engineers have a long learning curve.

Brian Bailey (Independent Consultant): SystemC adoption was held back by the lack of an adequate interface standard. TLM 1.0 did not provide model portability or compatibility. TLM 2.0 went a long way in rectifying that situation. It is not perfect, but it is good enough to get all of the system-level virtual prototype vendors adopting it. That removes the biggest impediment to ESL adoption, which was the availability of models. No vendor could afford to produce all of the models necessary themselves.

Steve Brown (Cadence): There is a need for a methodology that enables TLM to be the golden source for design. Otherwise, the full benefits of TLM synthesis aren't realized because functional verification must happen at the RTL level. In addition, the industry needs a strong IP eco-system for TLM design and verification IP that supports the methodology, similar to the RTL IP eco-system.

Andreas Ropers (ARM): First, it is crucial that abstract IP models based on SystemC / TLM-2.0 are available together with RTL blocks. These need to be provided by IP vendors. Second, design ideas are often manifested in RTL code, which is the typical abstraction level for hardware engineers. This make it complicated to provide an abstract model later on. Third, models still need to be integrated manually because the debugging of models is not addressed by SystemC/TLM-2.0. The lack of a standard to configure, control and analyze a model currently limits the usefulness of TLM-2.0 based models. At the moment, the ecosystem uses different proprietary solutions that imply high integration cost.

Question #3 | Introduction/Overview | Question #5