Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the fifth question: "What are the main use models for SystemC that are flourishing?"

Question #5: What are the main use models for SystemC that are flourishing?

TLM2 modeling - OSCI TLM2 standard - Four main concepts

Shabtay Matalon (Mentor): The main use models for SystemC are:

• ESL Design – Building an optimized transaction level platform
• ESL Verification – Validating and debugging the transaction level platform to meet system functional requirements
• Virtual Prototyping – Creating a Virtual Prototype that enabled Software validation and debug against an hardware model even before RTL

Laurent Ducousso (STMicroelectronics): Architectural exploration; SoC modeling for early firmware and software development; providing a reference for silicon validation and hardware verification; and high-level synthesis (HLS).

Simon Davidmann (Imperas): Users are looking to use SystemC/TLM2.0 where they need timing of transactions or behavioral components. Where they need high-speed programmers views, they tend to use fast Instruction Accurate processor models, such as those available from OVP (www.OVPworld.org) and use a platform written in C.

Nagendra Gulur Dwarakanath (TI): There's a "lot of SystemC" that goes into the development of architecture exploration tools. This typically comprises models that simulate traffic flows inside a chip or subsystem, via accurate models of memories, chip network topology and bus infrastructure. There's "some SystemC" that goes into the development of software simulators, and tools for high level synthesis. There's not much SystemC used in design verification. A challenge (and an opportunity) that exists in front of us is to bring these different uses of SystemC closer together.

Marc Schmitz (STEricsson): SystemC enables users to build:

• Software development platforms
• Co-simulation platforms used for verification purposes.
  

Ravi Venugopalan (Sonics): System C has the most applicability in complex SoCs that have many cores with high data performance requirements. Using SystemC will allow early modeling of the system to analyze data flow, identify bottlenecks, gate count, and power. SystemC is also used by OEMs to develop their systems which can then be passed on to semiconductor manufactures for silicon development.

David Beal (Virtutech): Early device-specific architecture design and firmware development.

J.C. Yeh (ITRI): Creating an executable specification.

Brian Bailey (Independent Consultant): Several of them have already been mentioned: providing a fast execution model for a system-level virtual prototype (SLVP); a reference model for verification; and as a high-level model suitable for synthesis.

Steve Brown (Cadence): Primarily reference models for simulation and SystemC for software development is the most active. High level synthesis is emerging and interest is strong to unify these use models with a common methodology. SystemC is proving to be superior to alternative languages such as C, C++, and Matlab’s “M”. The main reasons are SystemC can be used effectively for Virtual Platforms, High Level Synthesis, and Functional Verification with a single model. It provides the needed abstractions to model hardware including concurrency, and the ability to model different levels of timing.

Andreas Ropers (ARM): We currently see two main areas of interest: virtual prototyping and processor-driven verification. The limited visibility on the usage of SystemC for synthesis is most likely due to the fact that ARM co-develops the abstract models alongside the RTL rather than generating the RTL from the abstract models. With Fast Models, SystemC is purely used as an integration layer and not as a design language.

Patrick Sheridan (CoWare): At the SoC level, SystemC virtual platforms are used for architecture design and optimization, embedded software development and OS porting, and test bench development for system verification of RTL subsystems. Component IP modelers are using SystemC natively or they can easily wrap existing C models to enable their reuse in the SystemC virtual platform. Similarly, SystemC can be used by hardware designers within high-level synthesis flows. Beyond the SoC, the same SystemC virtualization technologies are being applied at broader definitions of the system: chip-sets and board-level subsystems, whole products and their operating environment, and even the distributed, networked electronic systems such those found in automobiles.

Question #4 | Introduction/Overview | Question #6