Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the seventh question: "What is the typical learning curve to an Engineer? Team? Company?"

Question #7: What is the typical learning curve to an Engineer? Team? Company?

Problems with today's design and verification flow

Laurent Ducousso (STMicroelectronics): This is difficult to answer because we have been on this journey for so long. It's probably fair to say that it is not trivial.

Nagendra Gulur Dwarakanath (TI): The answer depends on the role of the engineer. A simulation model developer is probably already proficient in SystemC and TLM. A hardware designer has a steeper learning curve – from RTL languages to C to C++ to SystemC. Design teams have begun exploring this learning curve through pilot projects. Here, putting a strong development methodology becomes extremely important to sustain adoption.

Marc Schmitz (STEricsson): It can take several weeks for an engineer to be able to build a platform with some guidelines, and several months to become autonomous. In a company, several years may be necessary to build an expertise and to spread good practice among teams.

Ravi Venugopalan (Sonics): For an individual engineer it takes three to six months. To fully establish SystemC models into a production flow can take a year. There are many integration challenges to be overcome.

David Beal (Virtutech): TLM as a concept and approach to modeling can be implemented using different languages. The level of difficulty to create these models is not a function of TLM as an approach, but on the flexibility and methodology embodied by the modeling language itself. As a C language template, SystemC lacks formality and even de-facto methodology to make it easy for engineers to adopt SystemC. Languages such as DLM supported by Virtutech Simics allow TLM methodology combined with a clear methodology to model creation.

J.C. Yeh (ITRI): I would say that the average is two months for a design engineer; six to nine months for a design team; and one to one and a half years for a company.

Brian Bailey (Independent Consultant): If they already know C++, then it is a small step from there to SystemC. If they only know C, then it is a larger learning curve and one that some engineers have found to be difficult in the past. While they may not be writers of it, they can still probably understand it enough to be able to work with it.

Steve Brown (Cadence): A design engineer that has C++ experience can expect to learn SystemC and TLM in a few days, and be proficient after their first project. Verification engineers typically have some experience with SystemC concepts already and have an easier time becoming proficient.

Patrick Sheridan (CoWare): For establishing a solid foundation of the concepts at the source code level, learning SystemC and TLM is more straightforward for model developers with a software background. However, this can be a challenge for hardware engineers that are not familiar with C++ or don't have prior software experience. To help with this foundation, industry training on SystemC and TLM is available from multiple training sources worldwide, both in online form or in a classroom setting, depending on the need. To ease standards-based TLM model development, commercial modeling tools available from CoWare can generate the SystemC TLM-2.0 interface code automatically so that novice modelers can concentrate on describing their functionality and timing in SystemC. For hands-on experience before a new project, commercial tooling that is SystemC TLM aware and provides examples of models suitable for the specific design task will definitely make ramp-up easier. For example, CoWare offers a downloadable virtual platform for embedded software development at: http://www.coware.com/solutions/vpdownload.php

Frans Theeuwen (NXP): For the engineer there are two new things to learn:

• SystemC is for hardware designers a new (object oriented language)
• In order to create efficient models, the engineer has to be aware that SystemC/TLM models are only efficient in execution and modeling time if not all the natty gritty details of for instance timing are modeled.

A design team has to be aware that the planning and activity order of the projects has to be changed. Software teams have to be available earlier than in conventional projects. Next to that, the hardware designers must be aware that last minute changes made in the hardware functionality will destroy the gain of early software development unless these changes are reported to the modeling team and the software designers A company has to be aware that introduction of SystemC based virtual prototyping needs an investment of a few years in order to develop an appropriate methodology and library of models.

Shabtay Matalon (Mentor): For a hardware engineer with an understanding of C++, the learning curve is very short. These individuals understand both the hardware concepts and the C++ concepts used by SystemC, therefore the learning curve is only for the semantics of using SystemC. For hardware engineers with little or no C++ experience and no object-oriented programming experience, it's really the C++ learning curve.

Question #6 | Introduction/Overview | Question #8