Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the tenth question: "Are SystemC synthesis and verification delivering on the promises of higher abstraction?"

Question #10: Are SystemC synthesis and verification delivering on the promises of higher abstraction?

TLM1 refresher- Abstraction levels

Marc Schmitz (STEricsson): High Level Synthesis methodology halves the development time. This is already verified with C synthesis. With its higher level of abstraction, SystemC can even improve this.

Ravi Venugopalan (Sonics): SystemC verification has existed for a decade now, but adoption and support is weak and hence there are not many takers. SystemC is delivering for sure on its promise for a higher level of abstraction with regards to building models.

David Beal (Virtutech): They are indeed delivering on this promise, but from the perspective of hardware developers. TLM or SystemC alone cannot solve all of the problems. The benefits of the Transaction Level Modeling approach extend far beyond hardware developers alone and to full system developers, especially when combined with other elements that make it usable for this audience – namely performance, adaptability, modularity, and standardized functionality and interfaces.

J.C. Yeh (ITRI): Maybe.

Brian Bailey (Independent Consultant): Absolutely. We still need better tools, but probably even more, we need better model portability in terms of control, debug, and other non-functional aspects. It is not clear that SystemC needs to move up in abstraction even more (as was originally intended by adding in an OS layer), but we do need to improve on what we have.

Steve Brown (Cadence): Our customers are able to benefit from both higher abstraction design and verification. The ability to perform functional verification using faster TLM simulation, and produce RTL much faster using high level synthesis is enabling an order of magnitude improvement in productivity for IP design teams. Once IP is designed and verified in SystemC/TLM, the ability to reuse the design and verification IP is multiplied because of the automation in creating and verifying RTL for new architectures.

Patrick Sheridan (CoWare): A clear strength of SystemC is its ability to support multiple levels of abstraction. Transaction-level modeling methodologies for virtual platforms support the loosely-timed, approximately-timed, cycle-accurate, and pin-accurate use of SystemC. This enables commercially available tool flows in the emerging area of high-level synthesis, as well as the established links to the mainstream OVM and VMM verification environments.

Frans Theeuwen (NXP): This is still a bit tricky at this moment. If you want to have SystemC models early in the design process, it is crucial that the time to develop these models is short, so a high abstraction level is needed. In order to get a high quality design out of behavioral synthesis, extra effort has to be spent to massage and configure the SystemC code for the synthesizer. If a balanced stepwise refinement approach is taken, SystemC synthesis can play a crucial role in future design methodologies.

Shabtay Matalon (Mentor): As a language, SystemC supports a wide range of modeling styles and abstraction levels: for instance loosely-timed (LT), approximately-timed (AT), or cycle-accurate (CA) to name only a few. Modeling in SystemC is therefore not a guarantee of abstraction. In fact, synthesizable SystemC typically relies on clocks and cycle-accurate descriptions. Such low-level models deny the initial promise of abstraction. This is probably why at the DAC 09 NASCUG (North America SystemC User Group), only 7.41% percent of respondents to a survey said they planned to use SystemC for synthesis, while 22.96% said they would use it for virtual platforms and 17.78% for system modeling. When it comes to high-level synthesis, the biggest benefits are obtained when starting from the most abstract models: the purely untimed ones. While this can be done in SystemC, it is most easily achieved starting from pure C++. From there, modern HLS tools will actually generate not only RTL, but also TLM and cycle accurate SystemC models to be used in subsequent ESL activities.

Laurent Ducousso (STMicroelectronics): SystemC and TLM are promising, but there is still a long way to go. They provide a good entry point for some specific design style, but RTL remains the level of exchange.

Nagendra Gulur Dwarakanath (TI): I am not the expert here. SystemC (or at least C-based) Synthesis seems to have gained ground across the industry. Point tools and custom languages may become out of favor. SystemC-based verification at the higher abstraction has a lot of potential for bootstrapping design verification far earlier in the design life cycle.

Question #9 | Introduction/Overview | Question #11