Recently, I got together with a bunch of folks to discuss the current state-of-play with regard to the use of SystemC and Transaction Level Models/Modeling (TLM). Here are the discussions relating to the eleventh question: "Is it possible to deliver virtual platforms using synthesizable SystemC IP?"

Question #11: Is it possible to deliver virtual platforms using synthesizable SystemC IP?

Abstraction Raises Productivity

Ravi Venugopalan (Sonics): I think it is, but there are lots of open issues that need to be resolved, such as clocking and the power domain, for example. SystemC coding guidelines for generating RTL that is area / timing / power efficient needs to be standardized and mature enough to be relied upon.

David Beal (Virtutech): This depends on how one defines "virtual platform". The performance limitations of SystemC quite dramatically impact complex virtual platforms consisting of a variety of elements. For complex virtual platforms that mirror physical boards, or systems made up of chassis and racks, the best approach is to use SystemC where it is best suited, for example on specific device models, combined with other approaches for the ISS, and other system devices. The overall system slowdown is not too great when the slow device is accessed infrequently and/or for very short periods.

J.C. Yeh (ITRI): This depends on the purpose of virtual platform; if this virtual platform is to be adopted for system-level verification, the answer is YES.

Brian Bailey (Independent Consultant): I am not sure why synthesizable makes much of a difference. I would simply say that: "Yes – it is possible to use SystemC IP in a SLVP, with some of the provisos already mentioned." Now, not all IP will be delivered this way. Some IP will be delivered as pure C or C++, which will still execute faster than SystemC and just have a wrapper around it. But the point here is that SystemC provides the integration fabric. As previously said the one problem for synthesis is that we do not have that synthesizable subset defined yet, so it is likely that models created for a SLVP will not be synthesizable.

Steve Brown (Cadence): Yes for three options: untimed or loosely timed models for synthesis (the synthesis standard needs to evolve to support this), and to extract automatically, or to automatically extract the virtual platform from the synthesizable model.  Certain types of models, such as processors, likely won’t be synthesizable in order to provide the needed performance through abstraction.

Patrick Sheridan (CoWare): Yes, this is possible today.

Shabtay Matalon (Mentor): It is of course technically possible to use synthesizable SystemC IP in a virtual prototype. However, since synthesizable SystemC typically requires clocks and cycle accuracy – especially to model interfaces – using such models will dramatically slow down the simulation performance of the virtual platform. A more efficient approach is to start from a purely untimed description, for instance in pure C++. From there, modern HLS tools can synthesize the needed RTL but also TLM and cycle accurate SystemC models which can in turn be used in virtual platforms. This methodology preserves the abstraction beneficial to synthesis and the simulation speed required for virtual prototyping.

Laurent Ducousso (STMicroelectronics): In theory the answer is yes, but it is not done today. Synthesizable SystemC is the output of a design process having a SystemC abstracted model. This first model remains in the virtual platform; transformations are then compared to the initial capture by formal tools or cosimulation.

Nagendra Gulur Dwarakanath (TI): This is a good question. In some sense, it is everyone's dream to get to that "one model" that is the golden reference, can be synthesized from, enables design verification, and is suitable for virtual platforms. In reality, it is perhaps two models (and not three or four). In general, algorithmic/signal processing models used for synthesis tend to be more amenable to be delivered for virtual platforms, unlike control/communication intensive IPs. It boils down to a question of the speed (and higher abstraction) we need for virtual platforms versus the detail needed for synthesis.

Marc Schmitz (STEricsson): Yes, provided that platform performance is acceptable for development.

Question #10 | Introduction/Overview | Question #12