Sometimes you just have to laugh a little at the way in which acronyms are put together or products are named. I just say one that I thought deserved a little bit of attention. So look at the product name first – quite simply SATURN. Now this is a European collaboration project, initiated in January 2008. As with all such projects there were many countries involved and several languages that helped in the naming of this project. So what does SATURN stand for - SysML bAsed modeling, architecTUre exploRation, simulation and syNthesis for complex embedded systems. Now that is a real stretch!! But what about the project itself?

SATURN’s goal is to bridge the current gap between modeling and verification/synthesis in UML based designs of Embedded Systems that are equally composed of hardware and software. Europe has always been one of the main proponents for hardware-software co-design so I wanted to see exactly what this project was attempting to do.

The players: SATURN combines two tool vendors (Artisan and Extessy AG) with leading system houses (Intracom S.A. Telecom Solutions & Thales Security Systems S.A.S). The consortium also includes two major European Universities: Paderborn University & University of Cantabria.

Artisan has now announced the first technology solution to emerge from this project. This first phase of the project concentrated on hardware (FPGA) modeling. “By bridging the gap between modeling, verification and synthesis, of hardware and software in UML/SysML-based designs, SATURN will demonstrate a significant reduction in time-to-market for embedded systems,” said Paul Whiston, Project Manager for Artisan Software Tools. “This is being delivered through the combination of SysML and MARTE as a platform to integrate these models with a run-time environment for cross-domain verification as well as the automatic generation of both hardware (SystemC) and embedded software (C/C++) components.  The integration of these different abstraction layers will allow seamless integration at functional and target architecture levels. At this mid-point in the project we have delivered an initial version of the complete tool chain, from design to implementation on the target hardware with optional simulation.”

Developed in conjunction with the University of Paderborn (Germany), the UML/SysML-based hardware/software co-design solution utilizes an enhanced SysML profile linked to a SystemC code generator for Artisan Studio.  This generates executable SystemC which is then translated into VHDL for execution in an FPGA.  The generated code can also be used to simulate systems in the Artisan EXITE ACE™ environment, including hardware simulation. This co-design and code generation solution has been fully evaluated using two complex, industrial proof-of-concept cases studies – a smart camera system and an outdoor broadband wireless telecommunications system. These initial case studies resulted in 56% and 58% automatic code generation respectively, with the simulation behaving as the final FPGA implementation. With the added benefits of the modeling environment managing all of the code and the documentation, this technology offers great promise.

In the next phase, the environment will be expanded to offer target processor simulation for software and the simulation of the SystemC in the EXITE ACE environment.  The project will also use the MARTE profile for Formal System Design (ForSyDE), and develop a HetSC profile in conjunction with the University of Cantabria which will aid formal verification of developed systems. This will be evaluated using proof-of-concept case studies and is expected later in 2010.

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Brian Bailey - keeping you covered