In the high-level synthesis market there has been a long standing debate amongst the vendors as to which is the right language to use as input. While there isn’t much disagreement that C forms the base language, and this is what some vendors use, most have decided that the capabilities added by C++ offer a much more compelling language base. Synfora, in fact, recently announced their migration from C to C++. But that is where the agreement has stopped. I have seen language charts from all of the vendors and it always make me chuckle to see where they put SystemC. Some say that SystemC is a lower level of abstraction because it adds more detail, while other say it is higher because it enables additional things to be described that cannot be described in C or C++. Most of these differences are related to how the SystemC language is used. SystemC is capable of describing systems all the way from an untimed functional description to a cycle accurate model and everything in between.

Then there are arguments made about the predictability of results, especially when concurrency is added into the picture. SystemC is a very loose language and it easy to describe systems that become completely non-deterministic when concurrency is used. But at the end of the day, the definition of large and complex systems cannot be done without the introduction of concurrency. This is an important part of the system design process and it is the responsibility of the designers and architects to ensure that their systems are deterministic otherwise they are failing in their jobs, and probably their products.

This language debate has done nothing to help the adoption of high-level synthesis, just like it did nothing for the industry to be arguing about the relative merits for VHDL and Verilog. So today is quite a watershed for the industry. Mentor, who according to Gary Smith EDA is the leader in the high-level synthesis market, has joined forces with Forte and Cadence in the support of SystemC. Cadence and Mentor now claim that they can handle the complete range of input descriptions from pure C or C++, through untimed SystemC using transaction-level communications, to models that include full cycle accuracy.

So why is this range of descriptions necessary and what does this enable? When we are considering a block – and the complexity of the block is unimportant – there are often reference models available in C or C++. Standards, for such applications as audio, video, encryption, wireless communications etc are all defined in C or C++ and thus there is a strong desire to be able to import these descriptions without modification. But a system is composed of many blocks that are tied together through one or more communication fabrics. Each communication fabric comes with a lot of constraints dictated by protocol and detailed timing diagrams. If you want to be able to synthesize a system that contains these elements then you have to be able to handle these protocol blocks, or as Mentor did in the past, incorporate them from a library of pre-built elements. The addition of these protocols also adds explicit concurrency in the system, and this too needs to be modeled. SystemC provide a convenient mechanism for this.

So we now have complete C, C++, SystemC high-level synthesis solution being provided by two large EDA vendors and in addition both are adopting an interface mechanism based on the OSCI TLM standard. This would definitely seem to be the direction that the industry will migrate in. Both Mentor and Cadence will now be touting their solutions for the manipulation of these system-level descriptions to make them synthesis friendly and a common need that they now both share is for a synthesizable version of the TLM interface. The OSCI TLM standards were built for simulation and ignored many of the needs and restrictions for synthesis. Interestingly though, this is the first time that synthesis requires extensions to the standard to add concepts, such as reset, that were ignored.

According to Mentor “Recent surveys indicate that 80 percent of today’s SystemC users favor working on transactional models above the cycle accurate level, and today most ESL activities, such as architecture analysis and virtual prototyping, rely on TLM. By supporting a modeling style compatible with the OSCI TLM2.0 approach, the Catapult C tool offers strong ties with ESL flows, methods and tools—such as the Mentor Vista™ platform—for comprehensive ESL design, verification and synthesis.”

Mentor’s users are also praising the move. “Mentor's decision to add SystemC support to a proven high-level synthesis flow with Catapult C synthesis is very welcome,” said Takashi Hasegawa, Deputy General Manager, SoC Solutions Division, Common IP & Technology Development Unit, Fujitsu Microelectronics Limited. “We’ve made efforts for a long time for the standardization of SystemC, and also anticipate that this addition will enable us to handle an even broader range of application challenges and provide more flexibility in using Catapult C with Fujitsu-supplied silicon technology libraries for our mutual customers.”

“Mentor’s Catapult C tool provides the right balance between detail and abstraction of advantage by dual language. Its cycle-accurate SystemC support gives us fine-grain control over our design and ability to read legacy-synthesizable SystemC IP, while its unique support for SystemC-TLM provides the abstraction missing from other HLS tools,” said Yoshinao Umeda, President, PRIMEGATE Ltd. “We are confident that Catapult C will have a positive impact on not only our business, but also most of electronic and automotive businesses, and help our customers experience more success with their ESL flows.”

To find out more about the Mentor solution go to: http://www.mentor.com/catapult-systemc

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Brian Bailey – keeping you covered