Avnet kit lets you do FPGA design without RTL

Written by Kenton Williston February 10, 2010 Hits: 634 Favorites

0.0 (0)

I’m happy with what I’m seeing in Avnet’s new Virtex-6 FPGA DSP Kit. This kit is designed to give let you start doing DSP design without needing any FPGA expertise, and I think it meets that goal. The kit is tightly integrated with an evaluation copy of Simulink, which lets you churn out FPGAs using high-level synthesis (or as The MathWorks calls it, model-based design). High-level synthesis is clearly the future of FPGA design, and it has been shown to be easier than C programming for DSPs.

The kit comes with two example WCDMA digital up converter (DUC)/digital down converter (DDC) designs. DUC and DDC are two of the more common uses for FPGAs, so these are excellent choices for showing how the design process works. I like that the kit come with both Simulink and RTL versions of the DUC/DDC, as well as DUC/DDC design tutorials. These resources let you contrast and compare the high-level design approach with traditional RTL to get an understanding of both.

Here’s what’s in the kit:

Design Source files for RTL and Simulink
Top level system integration RTL source files
Simulation environment
Testbenches
Implementation environment
Complete steps and parameters for design synthesis
MAP, place and route and timing closure
Targeted reference design tutorials including recommended flows for design modification and integration

User reviews

There are no user reviews for this listing.

To write a review please register or login.

Written by :

Kenton Williston