As you may recall, a couple of months ago a penned a short article titled Got OCP? The Role of the OCP in Multicore Designs. A little while later, the folks at OCP-IP released version 3.0 of the OCP specification, and I'm happy to report that is seems to be being very well received by engineers in the trenches.

Just to make sure we're all tap-dancing to the same drum beat, let's remind ourselves that the Open Core Protocol International Partnership Association (OCP-IP) first leapt onto the stage in December 2001, so we're not talking about a "fly-by-night" operation here.

The OCP is the first fully-supported, openly-licensed, comprehensive interface socket for semiconductor intellectual property (IP) cores – over one billion "gizmos" have now shipped with the OCP inside them.  Meanwhile, the OCP-IP is an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the OCP.

The OCP specification is actually a superset of all the ways in which the designers of different cores may wish their functions to communicate. Using the OCP, it's possible to get different cores with different interface standards to "talk" to each other and – more importantly – to actually understand what they are all "saying".

A graphical representation of the way in which different cores
(fail to) communicate if you don’t use the OCP.

OCP version 3.0 became the official specification of record towards the end of 2009. This latest version contains extensions to support cache coherence and more aggressive power management, as well as an additional high-speed consensus profile and other new elements.

Cache Coherence
Processor cores in System-on-Chip (SoC) devices often use local instruction and data caches to improve performance and reduce power by storing frequently referenced storage locations in high bandwidth low latency local memories. The OCP 3.0 coherence extensions enable hardware-based coherence among the wide variety of heterogeneous CPUs, DSPs, accelerators and streaming input/output devices that characterize advanced SoCs.

Low Power Design
Creating chips that consume less power is now at the forefront of design considerations. There are a wide variety of techniques that can be employed to achieve this, including powering-down functional blocks when they aren’t currently in use. Of course each designer implements power-down in a different way, so if your chip includes IP from multiple sources, it can be tricky to manage the powering-down and powering-up of these blocks.

In order to address this, OCP 3.0 defines a new connection protocol that allows the power management hardware to disconnect the OCP interface without losing any transaction so the manager may then independently shut off power.

Thumbs Up
Well, I've recently been chatting to some designer friends who are working with OCP 3.0, and the consensus is that these extensions are well thought out and are jolly useful (they didn’t say "jolly useful" exactly, I'm using my words here).

Detailed technical articles on cache coherence and power management are available on the OCP-IP website (www.ocpip.org).