A couple of weeks ago I published a blog about Altera's forthcoming 28 nm FPGAs (see Eeeek! 28 nm FPGAs with 28 Gbps transceivers!). In Altera's press release they waffled on about creating new FPGAs with embedded HardCopy blocks. At that time I thought I understood what they were talking about, but it seems that there is MUCH MORE to this story...

Just to remind ourselves and to set the scene, part of Altera's original announcement included a graph that looked something like the following. With regard to the "Relative Scale" annotation on the vertical axis, I've always been dubious about graphs with unnumbered scales ever since I read a book called "How to Lie with Statistics", but that's a discussion for another day...

So, the idea is that if we start off with a Stratix FPGA implemented at the 40 nm node (represented by the two columns on the left-hand side of the chart), then we can achieve a certain density and it will consume a certain amount of power.

Moving from left-to-right, if we were to re-implement the exact same FPGA (in terms of its functionality and logic capacity) at the 28 nm node with "no innovations", then we would achieve a higher density and lower power. If we were to then embed HardCopy blocks in our FPGA (I'll return to this point a little later), then we would achieve still higher density and lower power. Finally, if we were to include "all innovations", we would achieve yet higher density and lower power (actually, I find that I'm still a bit "fluffy" when it comes to understanding what "all innovations" actually means, but that's by-the-by because the rest of what I have to tell you is exciting enough in its own right and my poor old brain can only hold so much information before it overflows and generates an exception error).

But, before we proceed, I cannot help myself ... "I R an Engineer" ... maybe it's just me, but I just realized that I think that the above graph is fundamentally flawed. I understand that when you annotate an axis with the term "relative scale" you can understand that axis to mean whatever you damn well please, but by default I still tend to think that shorter bars indicate "less" or smaller" while taller bars indicate "more" or "greater". On this basis, I think that this graph should actually be presented as shown below:

As we see, I've left the "Power" bars untouched, so the idea is that the power consumption falls as we move from left to right. However, I've swapped the "Density" bars to indicate that the density increases as we move from left to right. I know, I know, this is hardly worth bothering about because we all know what they were trying to imply, but this is the sort of niggly detail that keeps me up at nights (grin). But we digress...

The way things work with today's 40 nm devices
Here's the way things work today with Altera's existing 40 nm devices. It may be that we are planning on initially deploying a Stratix FPGA in our end product, but that if sales are higher than expected we can re-deploy future versions of the product with an equivalent HardCopy ASIC. Alternatively, it may be that we always intend to deploy the product with a HardCopy ASIC, but that we are going to use the Stratix FPGA to prototype our design (this also has the advantage that the software folks can start developing their firmware on real hardware in advance of the final HardCopy ASICs being available.

Irrespective of the scenario, we commence with a Stratix FPGA as shown on the left-hand side of the illustration below. This FPGA consists of the package and the silicon chip. The chip itself comprises programmable fabric (look-up tables and suchlike) and what I've called "configurable IP cores". By this I'm talking about hard cores that can be configured in a variety of ways – for example, a high-speed transceiver that can be configured to implement a wide variety of communications protocols.

As usual, please note that these diagrams don’t reflect an actual architecture – they have been thrown together by yours truly only to illustrate the point I'm trying to make.

Once our design has been verified in the FPGA, we can hand it over to the folks at Altera, and in the fullness of time they will return an equivalent HardCopy ASIC as shown on the right-hand side of the above illustration. As we see, the package (and pin-out) is the same as for the FPGA – which means we don’t have to re-spin our PCB – but the silicon inside the package is smaller and this new implementation is faster and consumes less power.

The way things will work with the forthcoming 28 nm devices
In the case of Altera's forthcoming 28 nm devices, if we wish, we can use the same flow as for the 40 nm parts ... that is, start off by realizing out design in an FPGA and then transfer that design into a HardCopy ASIC. Alternatively...

If we already know 100% how we wish some of the hard IP blocks to be configured, then we can ask the folks at Altera to embed these configured blocks in our FPGA (see the illustration below), thereby significantly increasing the performance and dramatically reducing the power consumption associated with these blocks.

But wait, there's more! If you already know what function(s) you wish part of your programmable fabric to implement (maybe you have some proven internal or third-party IP you used in a previous design), then you can also replace some of the programmable fabric in your FPGA with a hardened equivalent as shown in the illustration below.

This really is rather cool. Essentially this means that we will have the ability to request Altera to provide us with "Custom FPGAs". Of course, in the fullness of time we can still migrate these custom FPGAs into full-blown HardCopy ASIC equivalents ... but maybe we won’t wish to, because it may be that our new custom/hybrid FPGAs offer the best of both worlds...

So who are the targets for this new capability? Well, first of all there are the folks at Altera themselves, because this allows them to introduce new FPGA variants very quickly, and it also allows them to create market-specific devices like broadcast-specific, communications-specific, military-specific, and so forth.

Next, we have Altera's partners, who now have the ability to deliver an FPGA that contains their own custom hard IP. And, of course, we also have ourselves – the end users – who (as discussed above) now have the capability to lay our hands on an FPGA that has been tailored to our unique requirements ("I'd like mine in pink, please!").

I tell you, every day someone comes up with yet another cool concept and I think to myself: "What a good idea!" I wonder who first thought of this at Altera? I can imagine a meeting sometime in the past where some junior marketer or engineer put his or her hand up in the air and said in a quavering voice "What if we...", and the room fell silent as others looked at each other with a growing glow of excitement in their eyes...