By Loring Wirbel, communications analyst

Some network planner at Facebook is obviously ecstatic, since Cisco Systems Inc. introduced its uber-high-end Carrier Routing System 3 (CRS-3) March 9, featuring an aggregate throughput of 322 Terabits per second.  Notice the company is still using that “Carrier” moniker, even though the people that care the most about ultimate throughput are the social network barons running dedicated data centers.  Don Lee of Facebook was just at an Ethernet conference, complaining to stunned attendees that he just can’t get Terabit Ethernet at a decent price.

Well, Don, your direct interfaces may not be there yet, but at least Cisco gives you bargain route aggregation at an introductory price point of $90,000!  And each CRS-3 comes with a six-chip QuantumFlow Array processor and a guaranteed six-month or 10,000-mile replacement of all brake and accelerator pedals.  Such a deal.

Seriously, before mentioning speeds and feeds, I should praise the incomparable Scott Raynovich for live-blogging the Cisco press conference at his Rayno Report.  It’s not that the instant market analysis is so necessary, it’s just that Cisco CEO John Chambers’ come-to-Jesus pontificating has gotten so over the top, it’s useful to have Scott serve as real-time standup comic to poke holes in the proselytizing.  And someone needs to tell Cisco executives it’s wrong to call a session Q&A, when it’s just mid-level managers from Cisco interviewing each other.  You go, Rayno, this is not “new journalism.”

But, hey, let’s give credit where it’s due.  The CRS-3’s throughput is triple Cisco’s previous CRS systems, and 12 times that of Juniper’s highest-end core routers, as Cisco executives mentioned dozens of times in the March 9 soiree.  Apparently, line cards are upgradeable to 100-Gbit ports, though the company was a bit vague, perhaps because transceiver components are still awaiting standardization, and Cisco keeps a lot of its own 40G and 100G study work in the Interlaken Alliance under wraps.

But the heart of the action is Cisco’s latest ASIC design, the QuantumFlow Array.  In fact, the announcement really centers on the new chip set, because the processors are put in existing line cards that go into existing chassis structures from CRS-1.  Karl Denninger rightly spanked Cisco for sending out invitations to journalists and analysts of an announcement that would
“forever change the Internet.”  No wonder the stock went down after the press conference – chip-level improvements in packet throughput are cool, but are scarcely game-changers.

Cisco was not too forthcoming on details of the second-gen array, but keep in mind that the first generation, used in CRS-1 as well as ASR routers, used 40 cores in the central packet processor, and complex queuing engines in the related traffic management chip.  Cisco talks about the six-chip instantiation’s power-dissipation improvements, and one could guess that the processor hardwires support for features like MPLS/PBB translation, and possibly network coding.  We might wait a while finding out, however.  In the meantime, kudos to Raynovich and Denninger for doing their part to pierce a hype bubble gone wild.