This is seriously cool – I am very excited. Actually, I'm tremendously excited about all sorts of innovations that are taking place in programmable logic space ("where no one can hear you scream"). As far as I'm concerned, the programmable logic domain (FPGAs and related devices) is absolutely the place to discover the coolest technology going.

Just today, for example, the folks at Tier Logic announced something really, really interesting. When we're in the design phase, we need a high degree of flexibility, the ability to implement changes quickly, the ability to work with real hardware and ... ultimately ... a fast way to get to the market. FPGAs address these needs, but traditional FPGAs are too expensive for volume production.

By comparison, when we're in the production phase, we need low manufacturing costs and low power consumption and high reliability and high security. So ASICs are the best alternative for volume production, but traditional ASICs are risky, expensive, and time-consuming to develop ("costly to obtain, cheap to sustain").

Another consideration is creating an FPGA prototype and then migrating that prototype into an ASIC implementation. Different vendors have different solutions to this – some are better than others and I could waffle on for hours, but let's not (a) wander off into the weeds or (b) dilute the message from Tier Logic.

The point is that the folks at Tier Logic say that they have the answer to all our problems. In fact they do have an incredibly cunning solution – one of those ideas that is so simple (conceptually) that as soon as you see it you slap yourself on the head and say: "Doh! Why didn’t I think of that?"

Introducing TierFPGAs
Let's start at the beginning and build the suspense. Consider a traditional SRAM-based FPGA. We might think of this as a 2D FPGA, because both the user logic (including look-up tables, registers, memory blocks, DSP blocks, etc.) and the configuration SRAM cells are created in the same silicon:

The result is that a large proportion of the traditional 2D FPGA die is consumed by the configuration SRAM. This has several implications, not the least of which is the fact that the various user logic elements have to be spread out to make room for the configuration cells, which increases the length of the tracks between those logic elements, which increases the time it takes signals to pass through the tracks, which negatively affects performance. Another consideration is that when we come to convert the FPGA into an ASIC – in which all of the logic elements are closer together – the timing of our design will change.

So now let's consider the Tier Logic solution. In the case of the TierFPGA, what they've done is to separate the user circuits and configuration circuits into three-dimensional (3D) stacked layers. The user logic is implemented in the silicon, which has the standard metallization on top. In fact 90% of the process is standard CMOS as illustrated below:

The configuration cells are implemented using a standard LCD-based Thin-Film Transistor (TFT) process, which accounts for 10% of the process steps. These TFTs are implemented in amorphous silicon, which means they have low performance (not a problem because they are used only for configuration) and low power consumption (there's no leakage). (I would be very interested to hear how these larger TFTs behave in high-radiation environments – it might be that these devices are inherently radiation-tolerant with regard to their configuration bits, which are the bane of standard 2D SRAM-based FPGAs.) Reducing the configuration overhead from the base-layers of silicon allows Tier Logic to produce smaller, denser, faster, lower-power, and more reliable FPGAs. This means that if we were to implement a 3D TierFPGA device with the same capacity as a regular FPGA, it will be physically much smaller, which shortens the tracks, speeds the signals, and lowers the cost as illustrated below:

Another way of looking at this is that if you kept the same die size as your original 2D FPGA, your 3D TierFPGA could support a much greater capacity!

Introducing TierASICs
But wait, there's more (this is where things get really exciting). Just look at the image above and think about this for a moment. Suppose we want to convert  our TierFPGA into a TierASIC ... all we have to do is replace the programmable configuration circuitry layer with simple metal layer. And that's just what they do ... once the TierFPGA design is frozen and signed off, the bit-stream information is used to create a single custom-mask metal layer that replaces the SRAM programming layer, resulting in a cost-reduced TierASIC device for high-volume production as illustrated below:

As we see, the original ninth layer of copper metal becomes the configuration layer with straps to Vcc and Ground, and the entire process is 100% standard CMOS. The really cool thing here is that we don’t have to change our original FPGA design in any way. The resulting TierASIC is 100% timing-compatible, pin-compatible, and package-compatible (including parasitic). Thus, unlike any other type of ASIC conversion, the timing remains identical between the FPGA and ASIC, allowing zero-risk, zero-effort conversions.

Come on... you have to admit that this is very, VERY clever!

Industry-Standard Tool Flow
Although Tier Logic’s 3D structure is different from other FPGAs, users will be very familiar with the architecture and tool flow when they design with the Mobius tools from Tier Logic because they have the same features as existing FPGA providers and the design flow is exactly the same. New or existing FPGA designs are easily synthesized, packed, placed, and routed into Tier Logic devices using industry-standard design tools, such as Precision Synthesis from Mentor Graphics, combined with Tier Logic's Mobius design tool suite. Mobius tools also create the bitstream for TierFPGA devices and the metal-mask data for TierASIC devices.

As Tier Logic's CTO Raminda Madurawe says, "The innovation of Tier Logic's monolithic 3D-FPGA significantly enhances the value of programmable solutions. By moving programmable overhead into the third dimension, we improve cost, power, performance, and security – all of the drawbacks associated with traditional FPGAs – without losing programmability. We can remove this overhead completely from the device without altering implemented designs to offer users timing-exact, very-low-cost ASICs – something traditional FPGAs simply can't offer."

TierASIC Benefits

• Low NRE cost: <$50K
• Low unit cost: Up to 75 percent less than typical FPGA pricing
• Easy conversion from TierFPGA devices: no engineering effort and identical, timing-exact performance
• Fast time-to-volume: Four weeks to first delivery
• High reliability: Single-event upset (SEU) immune

Capital-Efficient Startup
Tier Logic was founded by FPGA process-technology pioneer Raminda Madurawe and is led by Doug Laird, formerly CEO of Cswitch and a founder of Transmeta. Matrix Partners and Walden International provided Tier Logic’s Series A funding and it is extremely unusual for a semiconductor startup to come to market and take initial orders while still on a first round of financing.

"FPGA startups, and semiconductor companies in general, tend to burn through a lot of cash. Tier Logic has been very cost-effective and careful with its funding," commented Doug Laird, President and CEO of Tier Logic. "Not only have we developed silicon and tools, but unlike most semiconductor startups, we also developed a process technology first. And we’ve already been granted over 50 patents on fundamental 3D concepts and architectures. All this has been achieved for less than $20 million."

Early Access Program
Tier Logic is making a special offer to customers wishing to get early access to its technology. TierFPGA devices will be sampling in Q2 of this year, with production qualified in Q4. However, TierASIC devices are available immediately and will be in volume production in Q2. Until the sample TierFPGA devices are shipping, Tier Logic is offering customers with existing FPGAs who wish to take advantage of immediate conversion to TierASIC devices a free NRE if they place an order for $50k or more of production. In addition, for an order of $100k or more, Tier Logic will also create a custom pin-compatible package to avoid customers having to alter existing PCBs. More information on this offer is available at www.tierlogic.com/launch.