Deployed on TSMC's 40 nm process, the folks at Tabula have just announced their new ABAX family of FPGAs, which are based on Tabula's 3D Spacetime architecture. ABAX FPGAs are claimed to offer unprecedented capacity and performance – rivaling that of ASICs/ASSPs – at volume price points.

As you may recall, a couple of weeks ago as I pen these words the folks at Tabula announced a new FPGA fabric that they call "Spacetime". At that time, they described this as "useing time as the third dimension to deliver unmatched capability and affordability."

To be honest, my knee-jerk reaction was to be less than impressed. Over the last few years I have heard many claims of promises and delights that sounded wonderful at the time, but which eventually faded away into the nether regions from whence they had come. Thus, in my blog on that announcement I remarked:

"...from what I can see, all I'm hearing are announcements of the delights that are to come ... the chips 'will offer this' and they 'will do that' ... one day sometime in the future. What I'm not hearing is that the tool chain is 100% in place and that real honest-to-goodness silicon is available."

Well I certainly feel a little silly now, because as you will see in my video below, the tools are in place and they do indeed have honest-to-goodness silicon ... I know because I am now the proud owner of an ABAX FPGA, which is warping space and time in my office as we speak.

A rose by any other name...
Before we leap headfirst into the fray with gusto and abandon, I do enjoy clever company names and product names. In Tabula's case, their company name is derived from the Latin Tabula Rasa, which means "blank slate". The folks at Tabula say that they chose this name because their devices are, in effect, "blank slates" for turning ideas into production silicon.

Meanwhile, the first calculating mechanism known to us is the abacus, which is thought to have been invented by the Babylonians sometime between 1,000 BC and 500 BC. The word abacus comes to us by way of Latin as a mutation of the Greek word abax. In turn, the Greeks may have adopted the Phoenician word abak, meaning "sand," although some authorities lean toward the Hebrew word abhaq, meaning “dust."

Irrespective of the source, the original concept referred to a flat stone covered with sand (or dust) into which numeric symbols were drawn. The first abacus was almost certainly based on such a stone, with pebbles being placed on lines drawn in the sand.

I know, I know ... just wind me up and watch me go. The point is that naming Tabula's new FPGA family ABAX is really quite clever, because something gets written into the sand (silicon), then a fraction of a second later it's wiped out and replaced by something new, and so on and so forth...

ASICs vs. FPGAs
Let's take this step by step, because otherwise it can make one's brain ache. There are currently two main technologies when it comes to implementing digital logic: ASICs and FPGAs (for the purposes of these discussions we shall take the term ASIC to encompass ASSP and SoC).

On the one hand, the fact that FPGAs are programmable means that they are great for design prototyping and rapid implementation. By comparison, ASICs offer higher performance, lower power, higher density to support more capabilities, and lower cost in high volumes. Actually, when you come to think about it, FPGAs and ASICs are almost diametrically opposed at every stage of the product development flow:

So this is what the guys and gals at Tabula set out to address – to create a new class of device that could provide the Holy Grail for electronics companies: programmability, high-performance, high-capacity, and affordability:

It all seems so simple when you say it quickly, doesn’t it? But is such a solution really possible. Well, before we delve deeper, it's probably worth noting that Tabula has an absolutely outstanding management team. For example, founder and chief technology officer (CTO), Steve Teig, has been the CTO of four other successful start-ups, and was also CTO at Cadence Design Systems. Tabula's chief executive officer (CEO), Dennis Segers, was CEO at Matrix Semiconductor (which was a pioneer in 3D memory ICs) and "the father of Virtex FPGAs" at Xilinx. And the rest of the team read like the "Who's Who" of FPGA space – they even have a "token Altera guy" (Alain Bismuth, who used to be the vice president of HardCopy ASICs at Altera).

One interesting point is that, as Steve Teig told me, the folks at Tabula fully plan on being "A Leadership Company" – they want to be right up there with Xilinx and Altera – they have no interest in being #7 or #8. Bold words indeed, but is this possible? Well it might just be as we shall see...

The Spacetime fabric
OK, this is where we come to the interesting stuff. When you come to think about a conventional "2D FPGA", about 80 to 90% of the device is consumed by the interconnect, which negatively affects power consumption, performance, and capacity. A very simplistic view of Tabula's idea is that they use a smaller piece of silicon that they reconfigure eight times for each user clock beat. These reconfigurations are referred to as "folds".

For example, let's say that you have a user clock running at 200 MHz. Inside the ABAX, tabula have their own clock running at 1.6 GHz, so there are eight of their clocks for each user clock. Now let's consider a logical element like a look-up table (LUT). This can be reconfigured on each of Tabula's clocks, which means that it can be visualized by the user to be eight separate LUTs.

Arrggghh... I'm really not explaining this very well, because the user doesn’t have to visualize anything. As we shall see, this is all totally transparent to the user. The only thing they see is a low-cost, high-performance, high-capacity device that uses exactly the same RTL as any other FPGA, but we digress...

So our first-pass reaction is: "Cool, we only need to use 1/8 of the silicon." But then we remember that we need to store the eight different configurations associated with the eight folds. How much space does this take? Well, when you take everything into account, Tabula's Spacetime fabric ends up consuming only about 1/3 the silicon real-estate of a regular 2D FPGA of the same capacity. Furthermore, the Spacetime fabric ends up being much more routable, and its tracks are 78.5% shorter than in a regular FPGA, which means that timing closure is much, much easier.

Actually, there are two ways to think about this, because we can either use the Spacetime fabric to achieve the same capacity as a regular FPGA with only 1/3 of the silicon ... or we can use the same amount of silicon as the regular FPGA to achieve a much higher capacity. As one quick example, the biggest-and-baddest regular 2D FPGAs boast user SRAM blocks of around 20 megabits. By comparison, EVERY member of the ABAX family offers 5.5 megabytes, which is more than TWICE the amount!!! (I know, I know, multiple exclamation characters are the sign of a deranged mind, but I really am quite excited by all of this.)

Quite apart from anything else, the folks at Tabula have come up with all sorts of cool terminology, like their "time vias" that are implemented using transparent latches and which we might think of as wires that can store a reusable state. The resulting "spatiotemporal" routing architecture can transmit signals within a fold or between folds, or it can hold signals in place for use by multiple folds if needed.

In fact there are so many implications to the Spacetime fabric that it makes your head spin. For example, regular FPGAs have two-port SRAM blocks. By comparison, ABAX FPGAs boast eight-ported RAMs that are built from single-ported physical RAMs.

But wait, there's more! I don’t quite understand this bit (I'm still trying to wrap my brain around it), but if you manipulate the folds in a certain way, you can boost up the performance of your logic from 200 MHz to 400 MHz, or 800 MHz, or even 1.6 GHz. This is a tradeoff between capacity and performance, but the exciting thing is that you don’t have to do it for the entire chip – you might have the majority of the user logic running at 200 MHz, but then have different portions running at higher clock frequencies (when I actually understand this I'll explain it in more detail in a future blog).

And there's yet more, because when it comes to implementing a soft CPU core, the way in which the Spacetime fabric is architected means that we can implement all sorts of mega-cool capabilities that are usually associated with high-end hard cores, such as multi-threading, speculative execution, out-of-order execution, and so forth.

The Spacetime Compiler
As I mentioned in my previous blog, one of my concerns was whether or not Tabula had a tool chain in place, because a lot of other start-ups have produced cool hardware architectures in silicon but have fallen at the final fence due to lack of tools.

Steve (Tabula's CTO) explained that they were more than aware of this fact. Thus, once they had come up with the idea for their Spacetime fabric, their first step was to establish a software team to start developing the tools to make sure that it was actually possible to design with these devices.

The result is the Spacetime Compiler, which has the splendid attribute that it makes the underlying Spacetime fabric completely transparent to the user. The Spacetime compiler takes regular RTL (written in Verilog or VHDL) and standard Synopsys Design Constraints (SDC) as input, performs synthesis and spatiotemporal place-and-route, and generates the configuration file that will be used to program the ABAX chip (I have no idea if the folks at Tabula have a cool name for this configuration file ... but if I was a betting man I would bet that they do).

The ABAX family
This is where "the rubber meets the road". Initially, there are going to be four members of the ABAX family. The first to hit the street will be the ABAX A1EC04 – this is the device that is currently sitting on my desk.

Just look at these specs! The smallest device in the family has 220,000 LUTs, for goodness sake! By comparison, the largest member has an eye-watering 630,000 LUTs! All of the family members boast 5.5 megabytes of RAM, 44 PLLs, and 48 6.5 Gb/s SerDes channels. Furthermore, all members of the family have 920 regular I/Os, which makes migrating a design from one device to another as easy as it can be.

But the real shocker is the price. The smallest member of the family – the ABAX A1EC04 – is only a tad above $105, and remember that this is still a "honking" big device when it comes to capacity and performance. Meanwhile, the Big Kahuna of the family – the ABAX A1EC06 – is only $200, which is a fraction of the cost you would expect to pay for a top-of-the-line device from the other FPGA vendors.

The end result is that – based on Tabula's Spacetiem architecture – the ABAX family of devices enable high-performance, compute-intensive applications on a programmable platform at volume price points. Providing programmability in applications historically served only by ASICs or ASSPs, ABAX represents a new category of programmable logic device. ABAX resets the bar for the capability and density of programmable logic, memory and signal processing while maintaining a familiar design flow. Designed for a wide range of applications, ABAX devices will initially target the telecom, enterprise, and wireless infrastructure markets.

"For decades, the Holy Grail for electronic system manufacturers has been a logic platform that combines programmability and flexibility with large capacity and cost effectiveness. Semico believes that the unique approach to how Tabula accomplishes this is truly innovative and is something the entire semiconductor industry should take note of," said Richard Wawrzyniak, Sr. Market Analyst at Semico Research Corp. "Tabula's benchmark results for ABAX show significant advantages in both density and capability for logic, memory and signal processing when compared with 40 nm FPGAs, enabling ABAX devices to offer programmability both in traditional FPGA applications and beyond."

Deployed on TSMC's 40 nm process, ABAX devices integrate a rich mixture of fully configurable, high-performance I/Os, including 920 general-purpose parallel I/Os, and 48 6.5Gbps serial transceivers. To improve time to market and productivity, the ABAX family's design flow closely resembles those for FPGAs and ASICs, using synthesis, placement, and routing to compile designs from RTL into silicon.

In addition, ABAX devices support a broad portfolio of soft IP cores, including DDR2 and DDR3 memory controllers, PCI Express, Gigabit and 10 Gigabit Ethernet, soft CPUs, sRIO, CPRI, and OBSAI.

"We are proud to announce our 40 nm ABAX family of Spacetime 3PLD devices," said Dennis Segers, Tabula Chief Executive Officer. "We believe the combination of our breakthrough Spacetime architecture, our commitment to advanced process technology nodes, and our focus on standard design flows set Tabula and ABAX apart in the market. With the support of a seasoned executive staff, a world-class engineering team, and a premier investor group, we look forward to demonstrating to customers the value ABAX can bring to their applications."

ABAX Pricing and Availability
ABAX A1EC04 samples will be available in Q3 2010, and will go into mass production in Q4 2010. Pricing in 2010 for the A1EC04 is $150 for orders of 2,000 units.