By Loring Wirbel, Communication Analyst

The realm of 10-Gbit/sec network interface cards continues to be one of those eclectic environments where the speed of co-processing is determined by the silicon, yet the preferred deliverable is the NIC itself.  This has allowed Chelsio Inc. to be a continuous silicon innovator, while being recognized as a board-level innovator in TCP Offload Engines and iWARP protocols.

Talk to the physical-layer semiconductor folks, and all they seem to think about is 40- or 100-Gbit follow-ons to 10G Ethernet, despite the fact that 10G Ethernet took almost a decade to replace Gigabit Ethernet because of the issue of enterprise utility of all that speed.  Developers working on server virtualization understand there is still a daunting task ahead in unifying the storage network, dominated by Fibre Channel protocols, and the Ethernet-based data center.  That’s what Chelsio focused on in its Terminator 3, or T3 ASIC.

Kianoosh Naghshineh, president and CEO of Chelsio, said that there were no radical new protocol issues in moving to T4, but a demand for more efficient handling of Fibre Channel Over Ethernet (FCoE) protocols, even while keeping TCP offload processing front and center.  Chelsio’s answer was to implement a programmable Very Long Instruction Word protocol engine in the new T4 ASIC, while embedding virtualization support, four separate Ethernet MACs, and a special interface for PCI Express Gen 2.  It’s probably also worth noting that T4 includes a ternary CAM block, not unlike the TCAM in the recent Netronome NFP-32xx introduction, which spotlights the continued role pattern-matching and CAM memory play in higher-layer Ethernet protocol processing.

Think the packing of all this functionality in a 672-lead FCBGA will make it more likely Chelsio will license its ASIC design or sell chips directly?  If anything, trends seem to be moving in the other direction.  Chelsio already has diversified into a special “Bypass Adapter” card for specialized markets in deep packet inspection and monitoring.  For standard PCI Express implementations, the addition of new hypervisor and iWARP functions in the T4 ASIC actually make it more likely that the server and ISP central-POP communities will ask for board-level products.  If you’re not prepared to examine system-level implications of processing packets at seven layers in the OSI protocol stack, offering a naked T4 ASIC to the networking community might be putting power in the hands of fools.