ITRS Roadmap and Formal Verification: Jasper Design
 |
4.0 (1) |
Has anyone lately analyzed the latest ITRS report? Important implications for formal verification!
http://www.itrs.net/Links/2009ITRS/Home2009.htm
Has anyone really analyzed the latest ITRS report? Important implications for formal verification!
http://www.itrs.net/Links/2009ITRS/Home2009.htm
The ITRS roadmap published in Dec 2009 stated the need for formal verification, over simulation, as an essential technology for increasingly complex designs….showing an increasing % of bugs found with formal. Their analysts find that formal verification is a mandated technology….especially since the design complexity gap can be addressed by IP… but the verification gap remains the challenge! And an increasing challenge at that…
Actually, some Jasper customers are anticipating this roadmap by 4 years! In terms of the percentage of bugs found with formal verification (including both property checking and equivalency checking.) Because their designs are the most complex found today, they have anticipated the formal verification adoption curve to the year 2014! It is worth a note.
Your comments appreciated!
User reviews
Average user rating from: 1 user(s)
ITS Roadmap and formal - spreading the technology via classes
| Overall: | 4.0 |
Reviewed by Vivek SagdeoApril 02, 2010
Top 500 Reviewer
Comments (0)
View all my reviews
Report this review
Hi Holly,
The ITRS roadmap is interesting and the importance of formal verification as a design productivity enhancing technology is a hope and promise that can be fulfilled. Even then, when I work in verification in the chip industry, I do not see the momentum picking up in this direction as much as its promise.
Formal has a lot of promise and it can become a block level verification technology. With SystemVerilog, and OVM/VMM/UVM there is a direction in which engineers are writing classes with constraints for constrained random testing. In this methodology, there is no participation from formal verification vendors. If we come out with classes that are reusable and are formal compliant, it will enable spreading this technology to the mainstream RTL design and verification engineers.
Vivek
