The process of creating a configured processor core for a specific application can be highly automated. Compilers are now available that can examine the C code for a particular task or algorithm and suggest process extensions that will speed up that task or algorithm. These compilers can provide near-immediate feedback to a design team, which can significantly shorten the design cycle.

For example, Tensilica's XPRES Compiler can automatically analyze C code, identify critical inner loops and other tuning opportunities, and create many trial processor configurations with customized extensions that boost performance. The XPRES Compiler creates a graph showing different execution speed/gate-count trade offs for the analyzed code. That way, the design team can decide what trade-offs it wants to make between added gates (area) and increased performance (cycle count).

Tensilica's tool chain automates the process of designing a configurable processor. This automation allows Tensilica to guarantee that the results are correct by construction. The development process includes the following steps:

1. Compile the original C/C++ application and run the XPRES Compiler. The XPRES Compiler analyzes millions of possible instruction combinations and present the designer with alternatives.
2. The designer selects the "best" configuration for the target gate count. Optionally, the designer can manually refine the generated configuration.
3. Build the processor using Tensilica's standard Xtensa Processor Generator flow. The Xtensa Processor Generator creates an RTL description of the configured processor and generates tailored versions of all necessary software development tools including the compiler, assembler, debugger, and instruction set simulator. It also generates a C or SystemC simulation model of the proceswsor and EDA synthesis scripts. No manual work is required to match software development tools and processor.
4. Compile the original, unmodified C code to run on the customized processor core. It will take advantage of all customizations.

Note the if an ASIC designer uses the XPRES Compiler to create a customized processor, no modifications need to be made to the original C code or any other C code to use these new instructions. The compiler automatically exploits those new instructions.

Adding functions to a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. Configurable Xtensa processors are always compatible with major operating systems, debug probes, and ICE solutions; and always come iwth a complete, automatically generated software development tool chain including an integrated development environment based on the ECLIPSE framework; a world-class optimizing, vectorizing compiler; a cycle-accurate SystemC-compatible simulation models and instruction set simulator; the full industry-standard GNU tool chain; and EDA synthesis scripts.