The term software-defined radio (SDR) refers to a smart radio that automatically switches frequency spectrum and operational modes on-demand. This article provides an introduction to the history of SDR and the current state-of-play with regard to Military and Commercial SDR development.

Dr Joseph Mitola III is internationally recognized for his groundbreaking research into software radio and cognitive radio systems and technologies. Joe is credited with his original concept of cognitive radio in 1991, describing it as: "self-aware, user-aware, RF-aware, and (that) incorporates elements of language technology and machine vision."

Traditional analog radios are fixed in capability. Since all of their functionality is hard-wired into the radio, there is little ability to upgrade. Many modern radios add proprietary Digital Signal Processing (DSP) chips to traditional analog radio architectures to provide signal-processing functions with limited or no capability to upgrade. SDR is an alternative radio communication system, whereby components that are traditionally tasked and implemented in hardware (e.g. detectors, mixers, filters, etc.) are now implemented using software in PCs or embedded computing devices.

Today, an SDR system is typically comprised of a PC with a sound card, or an embedded Analog-to-Digital Converter (ADC) with an RF front-end. Signal processing is handled by a general-purpose processor and an FPGA, rather than being done in special-purpose hardware. While the concept of SDR is not new, the evolving capabilities of digital electronics are making rapid economical progress in many practical applications that were once considered theoretical.

An SDR can intelligently switch from crowded parts of the spectrum to less-used regions, or ramp up error-correction capabilities to overcome radio interference, while also tracking the user's location and making decisions based on predictive analysis. Software radio has significant utility for military and cell phone applications, for example, which must serve a wide variety of changing radio protocols in real time. The Federal Communications Commission has recognized SDR and cognitive radio as an efficient and practical means of re-allocating and better-utilizing licensed radio spectrum.

SDRs can receive and transmit widely different radio protocols (referred to as waveforms) based solely on the software used. All wideband broadcast channel modulation forms are first captured by Analog-to-Digital Converters (ADCs), and then "re-defined" in software. The receiver extracts, down-converts, and demodulates the channel waveform on a general-purpose processor and generates new waveforms as sampled digital signals. The waveform is then converted to analog via a wideband Digital-to-Analog Converter (DAC) from IF to RF.

In practice, a Universal Software Radio Peripheral (USRP) allows a general-purpose computer to function as a high-bandwidth radio, serving as the digital-baseband IF section of a radio communication system. The USRP enables engineers to easily design economical systems on a low budget with minimal effort, since a large community of developers and users have contributed to a substantial code base and provide many practical applications for the hardware and software. This powerful combination of flexible hardware, open-source software and a community of experienced users make it an ideal platform for software radio development. The basic design philosophy behind the USRP is performing modulation and demodulation waveform-specific processing on a host CPU. High-speed general-purpose operations like digital up/down conversion, decimation and interpolation are done on an FPGA. (Detailed software information can be found at http://gnuradio.org/redmine/wiki/gnuradio/UsrpFAQ)

In the simple USRP block diagram shown in Figure 1, all the ADCs and DACs are connected to an Altera Cyclone FPGA. This piece of the FPGA (using C++ and Verilog) plays a key role in the USRP system. Basically, it performs high bandwidth math to reduce the data rates sent to the CPU over a USB 2.0 bus. The FPGA connects to a USB Controller interface chip, in this example a Cypress FX2. Everything (FPGA circuitry and USB Microcontroller) is programmable over the USB.

Figure 1. Simple USRP Block Diagram
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The standard FPGA configuration includes Digital Down Converters (DDC) implemented with 4-stage Cascaded Integrator-Comb (CIC) filters as illustrated in Figure 2. CIC filters are very high-performance filters using only adds and delays.

Figure 2. USRP FPGA DDC
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For spectral shaping and out-of-band signal rejection, there are also 31 tap half-band filters cascaded with the CIC filters to form a complete DDC stage. The standard FPGA configuration implements 2 complete Digital Down Converters.

Also, there is an image with 4 DDCs, but without half-band filters. This allows 1, 2 or 4 separate RX channels. With 4 DDC implementation, in the RX path we have 4 ADCs, and 4 DDCs. Each DDC has two inputs, I and Q. Each of the 4 ADCs can be routed to either the I input, or the Q input of any of the 4 DDCs. This allows for having multiple channels selected out of the same ADC sample stream.

First, the DDC down-converts the RX signal from the IF band to the base band. Next, it decimates the signal so that the data rate can be adapted by the USB 2.0 and is reasonable for the computers' computing capability. The complex input signal (IF) is multiplied by the constant frequency (usually the IF) exponential signal. The resulting signal is also complex, and centered at 0. Then the signal is decimated with a factor N. The decimator can be treated as a low pass filter followed by a down sampler.

At the TX path, the story is pretty much the same, except that it happens inversely. A baseband I/Q complex signal is sent to the USRP board. The Digital Up Converter (DUC) will interpolate the signal, up convert it to the IF band and finally send it through the DAC as illustrated in Figure 3.

Figure 3. USRP DUC
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The Digital Up Converters on the transmit side are actually contained in the AD9862 CODEC chips, not in the FPGA (as shown in the figure). The only transmit signal processing blocks in the FPGA are the CIC interpolators. Interpolator outputs can be routed to any of the 4 CODEC inputs. In multiple TX channels (1 or 2), all output channels must be at the same data rate (same interpolation ratio). Note that TX rate may be different from the RX rate.

The USRP can operate in full duplex mode. In this mode, Transmit (TX) and Receive (RX) sides are completely independent of one another. The only consideration is that the combined data rate over the bus must be 32 Megabytes per second, or less.

Military SDR Development
The Joint Tactical Radio System (JTRS) is a program of the US military to produce radios that provide flexible and interoperable communications. Examples include reprogrammable hand-held, vehicular, airborne and dismounted radios, as well as base-stations (fixed, mobile and maritime). The goal is achieved through the use of SDR systems based on internationally-endorsed open Software Communications Architecture (SCA). This standard uses CORBA on POSIX operating systems to coordinate various software modules. SCA-based infrastructure software and rapid development tools for SDR education and research are provided by the Open Source SCA Implementation-Embedded (OSSIE) project.

The SCA, despite its military origins, is being evaluated by commercial radio vendors for applicability in various domains. However, the adoption and use of general-purpose SDR frameworks outside of military, intelligence, experimental and amateur radio applications is sluggish, because civilian users can more easily settle with fixed architecture, optimized for a specific function, initially being more economical in mass market applications. However, software-defined radio's inherent flexibility can yield substantial benefits in the long run, as fixed implementation costs of iterated redesign of purpose-built systems are being reduced, which explains the increasing commercial interest in SDR technology.

Civilian and Commercial SDR Development
One example of a vibrant commercial entrepreneur is Gerald Youngblood, an electronics engineer who's been an amateur radio operator since 1967.

Beginning in April of 2003, Gerald founded FlexRadio Systems as its CEO and President, to design and produce Software Defined Radio products, at first exclusively for the Amateur Radio market. The SDR-1000 was the outgrowth of four years of painstaking research and development, and was the very first complete Software Defined Radio (SDR) transceiver to interface with a Personal Computer for amateur radio use. It provided everything needed to convert a PC into a high performance, multi-mode 11 kHz-65 MHz general coverage receiver with 160-Meter to 6-Meter (1.8-54 MHz) Amateur Radio transmitting capability.

This is the first open source software, amateur radio transceiver to incorporate the scalable DSP performance of a personal computer (PC) and sound card to perform all modulation, demodulation, and control functions of the radio. The general purpose PC architecture now vastly outperforms even the best proprietary DSP chips, with cost/performance constantly improving. In addition, the professional audio market is driving significant improvements in sound card technology. The SDR-1000 takes advantage of these trends to provide upgradeable hardware and software performance.

Closely spaced two-tone third order dynamic range, combined with extremely low local oscillator phase noise is the primary factor that determines the performance of modern receivers. It incorporates a novel Quadrature Sampling Detector (QSD) that offers significantly higher dynamic range than traditional mixers (+99 dB). Further, by using single-conversion from RF to audio frequencies, other sources of nonlinearity are eliminated as compared to multi-conversion receivers. It uses a very low phase noise oscillator and direct digital synthesizer (DDS) to minimize reciprocal mixing with large adjacent signals.

The SDR-1000 is described in fine technical detail in a great four-part series in QEX Magazine called "A Software Defined Radio for the Masses", published by the American Radio Relay League (ARRL), and can be found on their website at http://www.flex-radio.com/News.aspx?topic=publications

In commercial markets, the FlexRadio Systems CDRX-3200 HF/IF Channelizing Digitizer is for applications such as signal intelligence and exploitation, geolocation, cognitive radio applications, and real-time signal analysis.

The CDRX-3200 channelizing digitizer leverages FlexRadio Systems SDR technology to provide up to 32 synchronous, 200 kHz bandwidth receiver channels – each delivering greater than 100dB two-tone, third order close-spaced dynamic range. The thirty-two channels on the CDRX-3200 can be tuned independently or synchronously over an input range of 100 kHz to 100 MHz. The output is streamed over Gigabit Ethernet using the VITA-49 communications standard. More information is available at their website.