A processor core’s main bus represents a significant I/O bottleneck – so much so that processor cores have lacked the I/O bandwidth required by many tasks performed in SOCs.

However, there’s a new breed of processor that relieves the congestion on the main bus by supporting other means for high-performance I/O. Tensilica’s Xtensa processors let you achieve data transfer rates that can match those of hand-designed RTL blocks. Tensilica offers four ways to directly communicate without using the main system bus.

1. The XLMI (Xtensa Local Memory Interface) bus is a simple, fast, single-cycle bus that performs data transfers much faster than the main system bus because it is not designed to support multiple bus masters. Instead, it can be used to tightly couple Xtensa processors used in dataflow instantiations, as well as integrate existing hardwired, high-performance complex state machine logic into the Xtensa processor’s memory space. It can be configured up to a full 128-bit width, delivering 3.2 GB/s (peak) low-latency bandwidth.
2. Ports act like GPIO (general-purpose I/O) and are wires that directly connect two Xtensa processors or an Xtensa processor to external RTL. Port connections can be up to 1024 wires wide, allowing wide data types to be transferred easily without the need for multiple load/store operations. Ports are particularly useful to convey control and status information.
3. Queues are like FIFOs and provide a high-speed mechanism to transfer streaming data without buffering.  Input queues and output queues operate to the programmer’s viewpoint like traditional processor registers, without the bandwidth limitations of local and system memory access. Queues can sustain data rates as high as one transfer every clock cycle or over 350 Gbits/sec per Queue added to an Xtensa processor.
4. Memory Lookup Interfaces are useful for connecting RAMS for table lookups or for connecting long-latency hardware computation units. Memories connected to these Lookup interfaces can be read and written directly from the processor datapath without using load and store instructions.

All of these features, when easily specified by the designer, are automatically added to the Xtensa processor and are 100% fully modeled by Tensilica’s Xtensa Processor Generator.  The full behavior of the interface is automatically reflected in the custom software development tools, instruction set simulator, bus functional model and EDA scripts. And because it’s automated using Tensilica’s patented technology, it’s pre-verified and correct by construction – no need to re-verify the processor.

Find out more by reading the white paper: Get Your ASICs and SOCs off the Bus!