It's no secret that I'm a big fan of GateRocket's FPGA verification technology in the form of the RocketDrive hardware and associated RocketVision software, so I was delighted to hear that the folks at Qualcomm have adopted these products to address the increasing complexity of the FPGAs and ASICs their engineering teams are developing.

Before we leap into the press release itself, let's briefly remind ourselves as to just what GateRocket's RocketDrive and RocketVision products are and what they do for us. Today's FPGAs are incredibly clever devices, but if you are new to using these little rascals, you may well discover that verifying your designs using conventional techniques can be harder than you think.

A traditional design flow
Let's first consider a traditional design flow. We start off by gathering all of the blocks forming our design represented at a relatively high level of abstraction (typically RTL, but IP from third party vendors may also contain behavioral constructs). We perform first-pass verification using software simulation and everything seems to be OK. So we synthesize the design, run place-and-route, load the configuration file into a real FPGA in the lab – and something goes horribly wrong. What do we do now?

The conventional approach is to take a WAG ("wild-assed-guess") as to where the problem originated based on how the design "crashed-and-burned," make some modifications and/or add some instrumentation to the RTL (like a virtual logic analyzer), re-synthesize, re-run place-and-route, load the new version into the FPGA, and re-run the testbench. All of this can take hours and hours and hours ... and the chances are that our design still doesn’t work.

So we cycle round-and-round making more modifications and adding more instrumentation until we eventually track down this bug and fix it (hurray!). But Wait! I don’t know about you, but my experience is that fixing one bug can uncover others, and off we go again. And the days turn into weeks, and the weeks turn into months (I'm imagining that scene from the film of H.G. Wells' Time Machine with the sun racing round-and-round across the sky – of course I'm talking about the 1960's version starring Rod Taylor, Alan Young. and Yvette Mimieux).

I bet you think I'm exaggerating. Well, a recent survey of FPGA designers undertaken by FPGA Journal (www.FPGAjournal.com) indicated that the traditional process for identifying and fixing FPGAs by looping from the lab (where the bug is first detected) back through simulation, synthesis, and place-and-route can add anywhere between 92 and 148 days to the FPGA development cycle! Eeeek!

The RocketDrive (hardware) and RocketVision (software)
OK, let's consider the technology from the folks at GateRocket. First of all there's the RocketDrive itself, which is presented in the form of a of a removable "caddy" that plugs into a standard 5¼" drive bay on a deskside workstation. RocketDrives come in a variety of models, each targeted toward a different family of FPGAs from Altera or Xilinx. In each case, the RocketDrive contains the largest member of the family with which you are working.

Each RocketDrive contains the largest member of the FPGA family with which you are working.

Now, let's consider a typical usage scenario based on the RocketDrive with its accompanying RocketVision software. As usual, we commence in the software simulation domain, verifying the design at a high level of abstraction. In some cases this new project will be based on a previous generation of the product and/or platform, in which case we will have access to a number of previously proven functional blocks. Using RocketVision, we can direct the system to place all of the previously proven blocks in the RocketDrive and keep the new blocks that are being developed in the simulator. This allows us to benefit from the acceleration of much of the design yielding dramatically faster simulation iterations. As each new block is completed, it is promoted to the RocketDrive.

Of particular interest is the fact that (a) unlike an emulator, all of the parameters associated with the design's Input/Output (I/O) pins can be downloaded into – and verified in – the physical FPGA in the RocketDrive and (b) unlike a development board, the design does not need to be modified in any way in order to use this technology.

OK, suppose we run into a problem. The original, high-level representation of the design works as planned in the software simulator, but – using the same testbench – the design fails when we promote one of the blocks into the physical FPGA in the RocketDrive. How can we isolate the problem and determine what's going wrong?

Well, as soon as a problem manifests itself, we can re-run the verification with the RTL version of the suspect block resident in the simulation world running in parallel with the gate-level version realized in the physical FPGA. By means of RocketVision, the signals from the peripheries of these blocks (along with any designated signals internal to the blocks) can be compared "on-the-fly."

Using this technology – combining conventional simulation with physical hardware and an appropriate debugging environment – it is possible to very quickly detect, isolate, and identify bugs, irrespective of where they originated in the FPGA design flow.

Of particular importance is the fact that we can choose which version of the block's outputs – from the software simulation of the block or from the hardware instantiation of the block inside the FPGA – we wish to be presented to the rest of the simulation/verification environment. This allows us to quickly add a "soft patch" in the simulation domain, verify that this addresses the problem, and immediately move on to consider the next bug. This means that we can address multiple bugs per day, and then run synthesis and place-and-route on a bunch of our "soft-patch" representations overnight.

The GateRocket approach can cut weeks from the in-silicon debugging process

By providing engineers with the ability to make multiple design-change-debug iterations in a single day, The folks at GateRocket say that this approach can reduce the number of RTL-to-bitstream iterations by 50%. The end result of RocketDrive and RocketVision is that design and verification engineers now have the ability to see how the design behaves in the physical chip running like it will in-system while still having access to all the capabilities and flexibility of a software simulator.

This technique allows engineers to quickly detect, identify, and correct differences between the original RTL and the physical chip. In addition to accelerating verification runs by 2X to 10X, this new approach reduces the in-silicon debugging process in half, saving weeks or months of valuable engineering time and resources, thereby speeding time-to-market (TTM) and time–to-profit (TTP).

Which brings us back to...
I tell you ... just wind me up and watch me go. Let's return to the fact that Qualcomm have adopted GateRocket's RocketDrive and RocketVision products to address the increasing complexity of the FPGAs and ASICs their engineering teams are developing. The original press release reads as follows:

Qualcomm adopted GateRocket after a comprehensive internal evaluation of the product’s capabilities, particularly in the area of simulation acceleration. Initial evaluations resulted in improvements of 2-11X with limited impact on their existing verification flows. The company uses FPGAs extensively in prototyping large ASIC designs, which often requires many FPGAs to be used as a prototyping platform. Performing long serial test sequences for such large-scale designs can run for days and are difficult to partition into smaller design portions. Design teams will use the GateRocket products on their FPGA prototypes as a way to more efficiently verify and debug internally developed IP, as well as system-level designs that will ultimately be implemented as ASICs.

"We’re expecting GateRocket to help us streamline the verification process by accelerating logic simulation for the FPGAs and reducing the number of errors we find in the lab, all without disrupting our current design flow," said Steve LoCicero, Senior Director of Engineering at Qualcomm. "The result is a much more efficient verification process for FPGA designs. We are pleased with the design cycle reductions made possible by GateRocket, and their support team has been extremely responsive in helping us adopt this approach."

A Streamlined, interactive verification process
Qualcomm can achieve silicon-level accuracy through the RocketDrive verification system which allows them to simulate their designs within the context of the FPGA device they are using. RocketDrive works seamlessly with Qualcomm’s functional verification environment, and allows designers to move effortlessly between RTL and the FPGA being targeted, combining actual FPGA hardware and RTL simulation models in the same verification run.

This technique provides engineers with the ability to make a change to one RTL block and re-run it along with the hardware representations of the other blocks, thereby avoiding the need to rebuild the FPGA for each fix and enabling multiple design-change-debug iterations in a single day.