Good Grief. The folks at Tier Logic have come up with a rather bold move, which is to take your existing FPGA designs from Altera or Xilinx and convert them into equivalent ASICs for FREE (by which I mean $0 NRE and free conversion).

As you may recall from my previous blog (Click Here to see that blog), Tier Logic is a startup company with a rather clever technology. Their idea is that a large amount of area on a typical SRAM-based FPGA is taken up by the configuration cells. So what they've done is to take these configuration cells out of the silicon (thereby dramatically shortening tracks, reducing delays, and increasing performance), and implemented them as Thin Film Transistors (TFTs) sitting on top of the highest metallization layer.

One benefit of this approach is to reduce power, because TFTs have almost zero leakage. The fact that they are bigger and slower than regular transistors doesn’t matter, because all they have to do is hold the configuration data. But the real advantage of this technique is that you can transition from your FPGA to a pin-identical, timing-identical ASIC by simply replacing the TFTs with a metallization layer that straps the configuration signals to logic 0 or 1 values.

But that's not what I wanted to talk about here... The reason for this blog is that Tier Logic are making a bold move to grab some market share. They want to take your existing Altera and Xilinx FPGA designs and generate corresponding Tier Logic ASICs. In the future they will charge for performing this conversion process, but at the moment the conversion is free ("what do you want for nothing, your money back?" as the old saying goes).

I've been bouncing emails back and forth with Paul Hollingworth, who is the VP of Marketing and Sales at Tier Logic (he's also a jolly nice chap and an all-round "good egg" as we say in England). In his most recent message, Paul told me:

I attach a one-page flyer we’re emailing to customers who are interested in the launch offer. It explains what the offer is and the terms. It’s as straightforward as I could possibly make it. Basically if they give us a production order of $50k or more, we’ll do the conversion and pay the NRE. If the order is for $100k or more, we’ll also do a pin-compatible package for them. If the unit price they’re paying is say $60, for a reasonable volume we might reduce that down to $25. So for a $100k order, you’re talking a commitment of only 4k units. That means over 4k units we would be saving them 4,000 x (60-25) = $140k – not bad for a trial. And if the parts don’t work as promised in their system, the order becomes null and void and they don’t pay anything.

Looking at This Flyer, I see that all you need to give Tier Logic is the RTL for your design along you’re your pinout files, timing constraints, and any test benches – they'll take it from there. The typical designs they can handle at the moment (they're coming out with larger devices later) are Cyclone and Spartan-class FPGAs with densities of 20k to 100k LUTs... and they've also done older Virtex and Stratix designs.

Zero Risk
The part I really like is the fact that there's zero risk – if the Tier Logic ASIC parts don’t work in your system, you pay nothing and you simply continue using your existing solution.

Furthermore, if you're worried about working with a startup, your designs can be placed in escrow with Toshiba, which means that should anything happen to Tier Logic, Toshiba will continue to manufacture the devices and supply them to you directly.

We certainly do live in interesting times...

Click Here to see the flyer