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Xilinx, Inc. - Reducing Switching Power with Intelligent Clock Gating by Frederic Rivoallon

Brent Przybus Written by Brent Przybus     May 26, 2010     Hits: 861     Favorites0 Add to favorites
 
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Xilinx introduces the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30 percent for Virtex®-6 and Spartan®-6 FPGA designs.

Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.

Click Here to view or download  this White Paper now!

For more information on products from Xilinx, please visit our homepage!

If you’d like to learn about the latest Xilinx webcasts and videos, please visit the Xilinx Webcast and Video Library page!

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