Thank Goodness! Finally! Someone has realized the importance of being able to create radiation-tolerant SRAM-based FPGA designs for high-availability and mission-critical applications.

Hostile environments
When most folks hear terms like "high-radiation environments," they tend to think of things like nuclear power stations or space applications, where the latter includes things like earth-orbiting satellites, those cute little rovers meandering their way around Mars, or deep-space probes on missions to Jupiter, Saturn, and the outer solar system.

In fact, many people don’t realize that radiation from one source or another is all around us. In addition to cosmic rays raining down on us from above, radioactive elements are found in the ground we walk on, the air we breathe, and the food we eat. Microwave ovens generate (you guessed it) microwaves, old-fashioned cathode ray tube (CRT)-based television sets and computer screens produce low-energy X-rays, smoke detectors contain small amounts of radioactive isotopes, and... the list goes on. (Before you start emailing me, I'm not saying that microwaves are 'ionizing' radiation – I'm just trying to set a scene – stop being so pedantic for goodness sake [grin].)

Even the materials used to create the packages for electronic components such as silicon chips can spontaneously emit radioactive particles. This was not a significant problem until recently, because the structures created in the silicon were relatively large and were not typically affected by the types and strengths of radioactive sources found close to the Earth's surface.

Increasing susceptibility of modern silicon chips
The problem is that – in order to increase capacity, increase performance, reduce power consumption, and lower costs – each new generation of silicon chips features smaller and smaller transistors. Today chips are commonly available at the 65 nm technology node; some devices are available at the 45 node and the 40 nm half node; and folks are working on forthcoming devices at the 28 nm node.

The structures on these devices are so small that they can be affected by the levels of radiation found on the Earth.  Radiation-induced errors can result in a telecom router shutting down, an automobile failing to respond to a command, an implantable medical device incorrectly interpreting a patient's condition and responding inappropriately, and so forth. These are just a few examples of many high-reliability or mission-critical systems that require designers to understand and account for radiation-induced effects.

I could waffle on about this for hours. In fact I'm currently working on a book that covers all of this stuff and that and considers the various techniques available to design and verify radiation-hard components, radiation tolerant-electronic designs, and radiation-mitigating software code. But we digress; this isn’t about me (or is it?).

Radiation and SRAM-based FPGAs
The point of all this is that some components tend to be more radiation-tolerant than others. For example, Antifuse-based FPGAs tend to be more radiation-tolerant than SRAM-based FPGAs. Having said this... SRAM-based FPGAs offer a lot of benefits, especially in the context of deep-space missions which can take years (decades) to plan and deploy. In recent times, NASA has discovered just how useful it is to be able to upload new code to microprocessors controlling equipment located far from home in order to correct errors or introduce new capabilities. And they are certainly aware of the potential benefits inherent in the ability to completely reconfigure an SRAM-based FPGA.

The downside is that – as I already noted – SRAM-based FPGAs tend to be susceptible to radiation events. Let's briefly summarize some of the unwanted effects that might be caused by a radiation event:

• Latchup (this happens in CMOS circuits when a heavy ion or a high-energy proton causes a short between the power source and substrate resulting in destructively high current).
• A flipping of a register bit; this is known as a single event upset (SEU).
• A glitch in the combinational logic, which is known as a single-event transient (SET). (If such a glitch is clocked into a register or memory element, it becomes an SEU.)
• A flipping of a bit in the on-chip SRAM memory (this can occur in any type of chip, including ASICs and Antifuse-based FPGAs).
• A flipping of one of the FPGA's on-chip SRAM-based configuration cells.
• A flipping of a bit in the off-chip configuration memory used to store the FPGA's configuration file.
• A flipping of a bit in some off-chip memory device that is accessed by the FPGA.  

The first case – latchup – is addressed at the physical level by constructing the chip in such a way as to prevent this condition from occurring; for example, using a Silicon on Sapphire process (in a worst-case scenario, the chip may have to be powered-down and up to clear the condition). Creating the chip using a special process of this type would be referred to as making the chip itself "rad-hard."

Handling errors in the external memory (configuration memory or user memory) is an issue unto itself. Our focus here is the errors that might occur in the SRAM-based FPGA itself. What we have to do is take a step back and say:

1. I know SRAM-based FPGAs are susceptible to radiation-induced effects.
2. I also know that using SRAM-based FPGAs offers substantial design benefits.
3. So what I need to do is to create my SRAM-based FPGA in such a way as to mitigate any radiation events. That is, to design the chip in such a way that it detects and corrects any such errors. This is known as making the design "rad-tolerant."

Hurray! The folks at Mentor have the solution!
Now, some folks do have some level of solution for this. The guys and gals at Xilinx, for example, have been doing some sterling work with regard to developing tools that can be used to implement triple-mode redundancy (TMR), memory scrubbing, and so forth. Having said this, however, as far as I'm concerned, the current "leader of the pack" is – without doubt – Mentor Graphics.

I'm delighted to say that the folks at Mentor have just announced their new Precision Rad-Tolerant FPGA design solution for aerospace and high-reliability applications. Developed with NASA’s guidance, this product introduces an industry-first, synthesis-based radiation effects mitigation solution to reduce the risk of functionality problems, including soft errors caused by single event upset (SEU) and single event transient (SET) disruptions. Initial support is available for SRAM, anti-fuse, and flash-based devices from Actel and Xilinx.

Creating rad-tolerant designs involves things like implementing triple-mode redundancy (TMR) for combinational and sequential logic, creating memory-scrubbing functions, ensuring state machines cannot perform illegal transitions between legal states, and so forth. Hand-coding these structures is expensive, resource-intensive, time consuming, prone to error, and increases the risks associated with the project. Having a synthesis tool that can do this automatically makes a huge difference. "Although the concept of TMR is simple, writing a reliable VHDL equivalent is not," says Melanie Berg, MEI Technologies, NASA/GSFC Radiation Effects and Analysis Group. "Automating TMR logic insertion, while allowing the user to select the type of TMR mitigation, is very beneficial to a FPGA designer developing critical space applications."

The Precision Rad-Tolerant product has several unique features that make it much easier for designers to incorporate a variety of radiation effects mitigation schemes, such as automated, multi-vendor, multi-mode Triple Modular Redundancy (TMR). The tool builds on – and enhances – proven mitigation methods such as redundancy of sequential and combinational logic. Because TMR insertion is performed at the synthesis level, designers are no longer limited to using fully radiation-tolerant devices and can achieve higher-quality results versus alternative mitigation approaches.

A unique feature of the Precision Rad-Tolerant product is synthesis-based insertion of fault-tolerant finite state machines (FSM). The resulting FSM can "absorb" radiation-induced single event upsets (SEUs), mitigating their effect rather than switching the state machine into an unknown or unpredictable state. This form of safeguard meets the needs of a wide range of high-reliability applications.

Even better, the Precision Rad-Tolerant solution also delivers all of the synthesis-based capabilities of Precision RTL Plus that we've grown to know and love, including low power synthesis, integration with other Mentor tools, and specialized features and flows for mil-aero and safety-critical applications.

It would be uncouth of me to drop vague hints indicating that I am a man who likes to keep his finger on the pulse; a man who is trusted by those who don the undergarments of authority and who stride the corridors of power; a man who is privy to all sorts of secrets; and – indeed – a man who has known about this product for some time – so rather than be uncouth and drop vague hints, I'll come right out and say: "I've known about this product for some time" (grin). In fact I've been "chomping at the bit" with excitement – desperately wanting to shout the news from the rooftops – so you cannot imagine how happy I am to be able to tell everyone that this solution is now available, speaking of which...

Product Availability
The Precision Rad-Tolerant product is available now. For more information on the Precision Rad-Tolerant product and other FPGA synthesis and mil-aero solutions from Mentor Graphics, visit the company website at: www.mentor.com/precision-radtolerant.