Brian Bailey’s must see list for DAC 2010
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4.3 (3) |
What an exciting DAC it will be this year. As someone who has been a leading proponent for all things ESL for a while now, and for so many years has been made to look a little silly, well, I do not need to hide my face in shame anymore. ESL is here now and getting stronger very quickly. There will be a lot to see in several important categories:
High-Level Synthesis
In the area of high-level synthesis, the market continues to grow and new capabilities are being added at a frantic pace. Most of the players are betting on C, C++ or SystemC as the starting point and they are:
- Mentor with CatapultC - 1383
- Cadence with C-to-Silicon - 1334
- Forte with Cynthesizer - 750
- AutoESL with AutoPilot - 1577
- Synfora with Pico - 770
Then there are those who want to skip the transaction-level altogether and start from a pure algorithmic description, such as MATLAB/Simulink. An example of this is Synopsys (581) with their Synphony product. And finally there is BlueSpec (1476) who have created a custom language. They strongly believe that this language provides significant benefits over the existing one.
Virtual Platforms
This list would have been long last year, but now it has shrunk considerably. The leaders include:
Wind River (Intel) with Simics who are not at DAC this year
- Synopsys (581) with an array of products from Virtio, CoWare, and VaST. It will be interesting to see how well they have started to integrate these together, plus brought in their concepts of hybrid prototyping
- Mentor with Vista (1383)
- Carbon (381) allows high level models to be created from RTL models which help take care of legacy issues.
Also take a look at Docea ( 1458) that has power modeling that can bolt on to these virtual prototypes through the use of trace files, and
CoFluent Design (1415) that has system modeling tools, and of course there is
The Mathworks (534), one of the biggest algorithm and system-level modeling companies out there.
Other ESL
- Duolog with Socrates for chip integration and HW/SW integration issues, and
- ChipEstimate (521) (part of Cadence) for chip estimation and planning.
Verification
- Zocalo Tech (1509) – with their assertion creation and control tools and
- NextOp Software (1442) with their assertion synthesis capabilities
In the formal space Jasper (1337) continues to come out with significant enhancements to their products including ActiveDesign.
Sequential equivalence checking is an important part of an ESL flow, and to find that you will have to go and see Calypto (286)
Newbies
One new company that I am eager to see what they have is Vennsa technologies (250) that claims to be able to automate debugging by finding the root cause of errors with no user guidance.
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Brian Bailey – keeping you covered
User reviews
Average user rating from: 3 user(s)
ESL to GDSII ECO flow
Brian,
It is indeed very exciting to see ESL pick up momentum, and I'm sure we'll start seeing more capbilities and flows around ESL being developed. One very unique capability Cadence has is a complete ESL to GDSII ECO flow. As anyone who has designed a chip (either at ESL or RTL level) would know, almost all designs go through ECOs and they can be very time consuming. Using Cadence's ECO flow, one can automate the process of ECO implementation and save valuable time. We'll be showing this at DAC this year (booth 1334).
Yoon
Cadence Best UVM demo at DAC
Hi Brian,
Just in time for the UVM, Cadence is back to DAC in a much bigger way than the previous years. For your readers, one thing I can highlight is the "Best UVM" demo in our Silicon Realization pod on the DAC floor in booth #1334. We have a wide array of technology and solutions from building the UVM environment, to running it fast, to analyzing and debugging the results. We'll even have something _new_, though I can't mention exactly what it is just yet. You'll have to stay tuned for a few more days!
Hopefully your readers will be happy to see Cadence back at DAC in a strong way and will stop by to see the news on UVM and the other Cadence offerings.
=Adam Sherer, Cadence Verification Product Management Director
Can you please add something on Emulation/prototyping products?
Hi Brian,
Interesting coverage on ESL & brief one on Pre-Si Verification (if you allow, here is my list/round-up www.cvcblr.com/?p=170).
Can you please cover the likes of EVE, HAPS, GateRocket etc.
Regards
Srini
www.cvcblr.com/blog





