There are some EDA companies that get lots of attention, and publicity in the main-stream press (read that as they pay money for advertising and thus also buy their way into having whitepapers etc placed). Then there are some companies that are so new, that it is difficult to find out anything about them. Then there is a final category of companies that have been around for a long time and yet never really seem to get noticed. Many of these companies have one or a few tools in a specific area rather than attempting to be providers of complete flows. A company that I would like to highlight today is Aldec. Did you know that they are one of the oldest EDA companies out there, surpassed only by Mentor Graphics (as far as I know. Do you know any others)? At DAC this year they celebrated 25 years in EDA. Happy Birthday and congratulations on being a survivor!

So what is new with them? A lot it would seem. Aldec concentrates on tools for front end design and verification and recently they have been catching up with the big boys on the verification front. At DAC they announced support for the  Open Verification Methodology (OVM) and the early release of the next industry standard Universal Verification Methodology (UVM) from Accellera.   OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 provides a pre-compiled OVM library and SystemVerilog simulator to help customers take advantage of this powerful design verification methodology to meet the challenge of verifying today’s complex designs. OVM has reached a level of maturity and stability and is the basis for the UVM assuring the long-term popularity and resulting in an increased support demand in a wide variety of tools.

Users of different levels of expertise can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment that can be reused across different designs and different platforms. Verification engineers will appreciate the flexibility OVM gives them and hardware designers will be satisfied that they can do advanced verification without going through advanced SystemVerilog training.

In addition, Aldec also provides an ASIC and SoC Transaction Level Emulation capability with bit accuracy. HES (Hardware Emulation System) is used by Aldec customers for emulation, acceleration and prototyping based on the existing prototyping hardware board from The Dini Group and Synopsys® HAPS™ , HES supports from 2 to 10 MHz SCEMI Emulation and up to 10X Acceleration for large complex ASIC & SOC designs from 1 Million to 32 Million ASIC gates.

Recently they also announced a tie up with Altium that brings together the Aldec verification suite with the Altium Designer tool suite to make a complete flow – particularly targeted at FPGA designers. Together they could become a formidable pair that could steal the show for FPGA design and verification.

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Brian Bailey – keeping you covered