Well, at long last, I can finally talk about a project that I have been working on with Cadence over the past year. It is yet another book, this time on the subject of a TLM-driven design and verification methodology as put together by Cadence. The book is being self published, and can be obtained from here.

So what is the book all about? It attempts to explain how to take a model, initially developed to be part of a system level virtual prototype, written in C or C++. This is a pure functional model with no communications defined. So it uses dedicated point-to-point channels. It also uses an adaptation of the industry standards TLM 2.0 interface, so those models are portable. Then, with minimum modification to that model, communications can be added and the system model refined. Additional enhancements can be made to the model, using SystemC, to add explicit concurrency if desired. The interface between the computation block and the communications block continues to use the TLM 2.0 interface. Then that combination computation plus communication block can be fed into the high-level synthesis process.

The book describes the whole process including both the verification of the block as it progresses through the flow and the way to get the best results from the synthesis process. Most of ther smarts came from my co-authors - Felice Balarin, Michael McNamara, Guy Mosenson, Michael Stellfox, and Yosinori Watanabe.

Chapter 1            Solution Attributes

1.1          The Process Today

1.2          Separation of Concerns

1.3          Abstraction

1.4          ESL and where TLM Fits

1.5          Mixed Control and Data

1.6          Design Team Roles

1.7          Power

1.8          Standards

1.9          Summary

1.10        References

Chapter 2            Languages for Transaction Level Design and Verification

2.1          Language Fundamentals

2.2          Languages for Hardware Modeling

2.3          Languages for Verification

2.4          SystemVerilog

2.5          Summary

2.6          References

Chapter 3            Introduction to the Cadence TLM Design and Verification Methodology

3.1          Introduction

3.2       Design and Verification Technologies Overview

3.3          Algorithmic Stage

3.4          Architecture Stage

3.5          Micro-Architecture Stage

3.6          The Future

3.7          References

Chapter 4            High-level Synthesis Fundamentals

4.1          Defining Synthesis

4.2          Concepts of high-level synthesis

4.3          Future Directions

4.4          References

Chapter 5            Using C-to-Silicon to Solve Real Problems

5.1          Good and bad descriptions

5.2          Synthesizable constructs

5.3          Concurrency

5.4          Making architectural changes

5.5          Inputs and Outputs

5.6          Register definition

5.7          Protocols

5.8          Memories

5.9          Integration with flow

5.10        Reports

5.11        ECO support

5.12        SystemC Synthesizable Subset

5.13        The Future

5.14        References

Chapter 6            Verification Fundamentals

6.1          Introduction

6.2          Metric Driven Verification

6.3          OVM Testbenches

6.4          Refinement Verification

6.5          Regression

6.6          Debug

6.7          HW/SE Co-verification

6.8          Hardware acceleration

6.9          FPGA Prototypes

6.10        The complete verification environment

6.11        The Future

6.12        References

Chapter 7            Verification Flow in Action

7.1          Introduction – Verification across abstraction levels

7.2          Verification Planning

7.3          Developing Multi-Level Verification IP

7.4          Verification across integration levels

7.5          The Future

7.6          References

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Brian Bailey - keeping you covered