In a recent blog titled Redefining Verification Performance (Part 2), Harry Foster from Mentor claims that in the next 10 years we will see a 10X increase in the number of transistors on a chip and 1000X increase in the necessary verification effort. He leaves it up to a future blog to talk about how to deal with this. First – I don’t believe that numbers is right. If we consider all parts of a design to be interacting with each other and that the entire state space of a design can be impacted by each and every input, then maybe this theoretical number is close, but that is not the way in which designs are progressing.

Designs are become more compartmentalized and with that we start to encapsulation and controlled communication. This is just like the progression of software development in the past. If we compared the size of a typical software program to the number of gates in a design, I bet the software design is many orders of magnitude larger, and while we all know that software does tend to have bugs, it is not the kind of bug rates we should expect if we applied a double square law to the verification effort required to minimize the number of bugs.

While Harry shows that first time chip success rates are going down, the number of people that are successful with one chip spin is increasing – almost to the 50% mark. I have talked to many companies and one chip spin is almost baked into their plans. Without real silicon they cannot do much of the software execution testing that they want to do, they cannot run long enough scenarios – and besides constrained random is just not up to the creation of those scenarios – so the first spin IS part of their verification strategy.

Now we may see some of that decline as system-level virtual prototypes become a reality. This will enable software to be executed earlier, and longer tests to be executed. We may also need better hybrid prototyping tools so that designs can actually be executed in-circuit, and it may bring about more rigor in the way that software is tested as well since it will now become a more integrated aspect of the chip development flow. That does not mean that independent hardware verification would not be necessary, as anyone who has ever read one of my books will understand, but it is certain that more integrated verification will be performed in the future.

So, part of the answer to the verification challenge in the future is to design systems that use more encapsulation, controlled communications and to create system-level virtual prototypes on which faster verification can be performed much earlier in the cycle and combine both the hardware and software systems.

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Brian Bailey - keeping you covered