48th Design Automation Conference (DAC) Issues Call for Contributions

First deadline: October 19, 2010
Design Automation Conference 2011

LOUISVILLE, Colo.--(BUSINESS WIRE)--The Design Automation Conference (DAC), the premier conference devoted to design and design automation of electronic systems (EDA), is seeking submissions that deal with tools, algorithms, EDA tool usage and design technologies for all aspects of electronic circuit, system, and embedded design for DAC 2011. In addition to conventional EDA topics, DAC 2011 invites submissions on Embedded Systems and Embedded Software topics. DAC 2011 also invites participation in various other EDA-related categories. This includes User Track submissions, Wild and Crazy ideas (WACI) submissions, Special Session, Panel and Tutorial proposals and co-located events.

New for 2011 is a strong focus on Embedded Systems and Software. Authors of Research Papers on all aspects of Embedded Systems and Software are specifically encouraged to submit their work to DAC 2011. Also new for 2011 is that select authors of submitted DAC papers that are not accepted for publication in 2011 will be invited in mid-February 2011 to participate in “Work-In-Progress” (WIP) poster sessions.

The 48th DAC will be held at the San Diego Convention Center in San Diego, California, from June 5-10, 2011. Submission criteria and topics – including new cross-cutting topics that include low power, 3-D, and reliability – are outlined briefly below.

All submission information and topic details can be found at: http://www2.dac.com/48th+call+for+contributions.aspx

Research Papers

DUE BEFORE 5:00pm MT, November 18, 2010

A DAC Research Paper explores a specific technology problem and proposes a complete solution to it, with extensive experimental results. Submission includes a six-page paper and an abstract of approximately 60 words clearly stating the significant contribution, impact, and results of the submission. Select authors of submitted DAC papers that are not accepted for publication in 2011 will be invited in mid-February 2011 to participate in “Work-in-Progress” (WIP) poster sessions. They will be asked to submit a 100-word summary to publish on the website (and not in the proceedings). The authors also will be given the option to post their poster presentation on dac.com.

Embedded Systems and Software Papers (new)

DUE BEFORE 5:00pm MT, November 18, 2010

Authors of Research Papers on all aspects of embedded systems and software are specifically encouraged to submit to this focus call. It is possible to choose a second submission category (both from the regular research topics as well as from the focus embedded topics) to accommodate cross-cutting contributions. Submission requirements are the same as for Research Papers, and authors of papers not accepted again may be invited to participate in poster sessions, as above.

“Work-In-Progress” (WIP) Abstracts (new)

DUE BEFORE 5:00pm MT, March 1, 2011

This track aims to provide authors an opportunity for early feedback on work in progress or to share early results through a poster presentation outlined in a one-page submission that clearly specifies a technical problem, outlines a solution, and provides some early results. A WIP submission will not be included in the DAC proceedings. Therefore WIP presentation at DAC will not be considered as DAC publications, enabling full publication of the work at a later stage. If accepted, the 100-word summary will be placed on the dac.com website and authors will be given the option to place their poster on the web in addition to the 100-word summary. WIP authors are at liberty to submit an extended version of their work to other conferences and to journals without violating common codes of ethics.

User Track Extended Abstracts

DUE BEFORE 5:00pm MT, January 11, 2011

DAC’s User Track addresses the real-life issues facing IC designers, application engineers, and design flow developers. It provides valuable insights and experiences with in-house or commercial EDA tool flows. User Track papers may describe the application of EDA tools to the design of a novel electronic system or the integration of EDA tools within a design flow or methodology to produce such systems. A User Track paper may be problem-specific in scope (e.g., analyzing substrate coupling during floorplanning) or may address a specific application domain (e.g., designing wireless handsets). Initial submissions are in the form of a two-page extended abstract. Final submissions will be in the form of a PowerPoint presentation. User Track authors will not be required to sign a copyright release form as final submissions will not be published.

“Wild and Crazy Ideas” (WACI) Short Papers

DUE BEFORE 5:00pm MT, November 18, 2010

DAC invites two-page submissions with genuinely forward-looking, radical, and innovative ideas in the area of electronic design or EDA. The WACI sessions feature novel (and even preliminary or unproven) technical ideas, with submissions that follow the rules and deadlines for Research Papers. The aim of WACI is to promote revolutionary and way-out ideas that do not fit the conventional mold, that inspire discussion among conference attendees, that create a buzz, and that get people talking. Research that incrementally improves on prior work is not suited for this category. All WACI accepted papers will be required to post a two-minute video describing the work as part of the acceptance process.

Special Session Proposals

DUE BEFORE 5:00pm MT, October 19, 2010

A special session is devoted to a topic of strong contemporary or future interest which represents an emerging area that does not yet receive sufficient focus from Embedded Systems and Software or Research Papers. Special session proposals must include descriptions of the proposed papers and speakers and the importance of the special session to the DAC audience. A submission must list at least three inspiring speakers who address the topic from different angles. DAC reserves the right to restructure all special session proposals. Particular topics of interest this year include, but are not limited to, embedded systems and software, spintronics, topological insulators for interconnect, and bio-design automation.

Panel and Tutorial Proposals

PANELS DUE BEFORE 5:00pm MT, October 19, 2010

TUTORIALS DUE BEFORE 5:00pm MT, November 1, 2010

Panel and tutorial suggestions should not exceed two pages, should describe the topic and intended audience, and should include a list of suggested participants. Tutorial suggestions must include a bulleted outline of covered topics. DAC reserves the right to restructure all panel and tutorial suggestions.

Workshop Proposals

DUE BEFORE 5:00pm MT, January 20, 2011

DAC invites workshops on topics related to design, design methodologies, and design automation. DAC provides the financial and organizational support, including attendee registration, rooms at the conference center and audio visual equipment.

Proposal for Colocated Events

DUE BEFORE 5:00pm MT, January 20, 2011

DAC invites companies to colocate their conferences, meetings or other special events with DAC. DAC will provide meeting rooms at the conference center at no cost. The event will be financed and otherwise organized by the submitter.

Student Design Contest

DUE BEFORE 5:00pm MT, November 24, 2010

Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2011) May 1-4, 2011 Pittsburgh, Pennsylvania, USA

http://www.nocsymposium.org

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip and in-package communication technology, architecture, design methods and applications.
NOCS aims at bringing together scientists and engineers working on NoC innovations from inter-related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation.

Original papers describing new and previously unpublished results are solicited on all aspects of NoC technology. Topics of interest include, but are not limited to:

* Network architecture (topology, routing, arbitration)
* Network design for 3D stacked logic and memory
* Mapping of applications onto NoCs
* Power and energy issues
* Timing, synchronous/asynchronous communication
* NoC reliability issues
* OS support for NoCs and programming models
* workload characterization & evaluation
* Network interface issues
* Modeling, simulation, and synthesis of NoCs
* NoC support for memory and cache access
* NoC design methodologies and tools
* NoC Quality of Service
* NoCs for FPGAs and structured ASICs
* NoC support for CMP/MPSoCs
* Novel interconnect links/switches/routers
* Optical & RF for on-chip/in-package interconnects
* Signaling and circuit design for NoC links
* Physical design of interconnect and NoC
* Verification, debug & test of NoCs
* Metrics and benchmarks for NoCs
* NoC case studies, application-specific NoC design

Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. Papers will be evaluated by the program committee in a blind review process based on scientific merit, innovation, relevance, and presentation. Proposals for tutorials, special sessions, panels are also invited. Detailed instructions for paper, tutorial, special sessions, and panel proposals will be available in a timely manner.

A special section related to the theme of the conference will be organized in collaboration with one of the IEEE journals.

IMPORTANT DATES

Abstract registration deadline Dec 10, 2010
Full paper submission deadline Dec 17, 2010
Proposals for tutorials, special sessions and panels Jan 14, 2011
Notification of acceptance Feb 18, 2011
Final version due Mar 11, 2011

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2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2)

Feb 12th 2011, San Antonio, Texas, USA

Held in conjunction with HPCA-17

http://hpca17.ac.upc.edu/saw-2/

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Organizing Chairs:

Ravi Iyer Intel Labs ravishankar.iyer@intel.com

Ramesh Illikkal Intel Labs ramesh.g.illikkal@intel.com

Raj Yavatkar Intel raj.yavatkar@intel.com

Overview

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Computing platforms are getting smaller (e.g. handheld devices), richer (e.g. visual computing applications) and broader (i.e. reaching the masses via smartphones and other embedded devices). This trend is made possible by System-on-Chip (SoC) architectures that combine high performance, ultra-low power general-purpose cores along with a wide spectrum of domain-specific accelerators or Intellectual Property (IP) blocks. With the recent introduction of general-purpose compute cores such as Intel® Atom™ processor, these platforms have the potential to run a much broader range of applications than ever before. The goal of this workshop is to bring together academic researchers and industry practitioners to discuss future SoC architectures, accelerators and workloads. The research challenges in SoC platforms are multi-fold, including: (a) providing rich functionality and high performance while maintaining ultra-low power, (b) attempting to cover a broad range of applications that can be migrated from mainstream platforms to SoC devices, (c) enabling a modular architecture and design environment that improves time-to-market and (d) providing a rich software programming environment that eases the challenge of developing applications on a heterogeneous architecture consisting of general-purpose cores as well as specialized accelerators.

Below is the proposed list of topics for the workshop. Topics include, but are not restricted to, the following:

* Novel SoC Architectures

- Ultra-Low Power Core Microarchitectures

- Heterogeneous Architectures and Multi-core SoCs

- Fabrics / Network-on-chip

- Cache/Memory Hierarchies

- HW Support for Programmability and Modularity

- Automated Design Environments

- Simulation / Emulation Methodologies

* Emerging Workloads

- New Workloads (e.g. Visual computing examples such as Augmented Reality, Multi-modal interfaces, etc)

- Workload Analysis for optimization and acceleration

- Workload Partitioning between Cores and Accelerators

- Performance Monitoring and Evaluation

- Case Studies of SoC applications

* Novel Accelerator Designs

- Specialized Accelerator Architectures and Designs

- Domain-Specific Programmable/Configurable Accelerators

- Accelerator Interfaces for Programmability

- Development Environments for Accelerator Design

- System-Level integration of Accelerators

* SoC Systems Software

- Modular Systems Software

- Heterogeneous Programming Languages and Environments

- Application Development Environments

- Runtime Libraries and Environments

Submission Guidelines:

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Interested authors are encouraged to submit extended abstracts (1 - 2 pages) or short papers (6 pages) by email to the organizing chairs (Ravi Iyer, Ramesh Illikkal and Raj Yavatkar). The deadline for submission is Nov 19th (by midnight in US PST zone). Final (short) papers will be due on Jan 10th 2011 and will be printed in a workshop proceedings made available to the workshop attendees.

Note: Best papers from SAW-2 will be also considered for subsequent publication in IEEE Computer Architecture Letters. More information on this will be available later.

Important Dates:

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Abstract / Paper Submission Nov 19th 2010

Author Notification Dec 20th 2010

Final Paper Submission Jan 10th 2011

Workshop Feb 12th 2011

DATE 2011 --- CALL FOR PAPERS

Grenoble, France -- March 14-18, 2011
www.date-conference.com

The 14th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community.
Special space will also be allocated for EU-funded projects to show their results.

The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia and automotive systems. Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics.

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SUBMISSION INSTRUCTIONS
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All manuscripts must be submitted electronically before

** September 5th, 2010 **

following the instructions on the conference Web page:
www.date-conference.com

DATE 2011 submission will open on 1 August 2010:

DATE 2011 - Conference and Exhibition
March 14-18, 2011
Grenoble, France

Submission Deadlines:

Sept. 5, 2010: Papers, Special Sessions, Tutorials, Workshops

Oct. 10, 2010: Exhibition Theatre

Nov. 12, 2010: PhD Forum

Jan. 14, 2011: University Booth

More Information:

Download/View the CfP as PDF here (PDF - 282kB)

Complete DATE 2011 information available on - www.date-conference.com