ESCUG: Call for Contributions - ESCUGM22 @ FDL2010 - Southampton, UK - Tuesday, Sept 14, 2010

Dear SystemC User,

We are pleased to announce the 22. European SystemC User's Group Meeting, which will take place co-located with FDL '10 in Southampton/UK at

Tuesday, September 14th, 2010, 18:00 - 21:00

Please mark September 14th, 2010 for our next European SystemC User's Group Meeting in your calendar. Detailed information and the invitation will be sent by email and will also be available on our web site:

www.ti.uni-tuebingen.de/escug

CALL FOR CONTRIBUTION (User's Forum)
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We will traditionally provide possibilities for SystemC users to present and discuss their experience with SystemC. Participants who are interested in presenting their work are very welcome and should send title and a short abstract until August 31st, 2010 to axel.braun@informatik.uni-tuebingen.de.

CALL FOR CONTRIBUTION (Supplier's Forum)
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We are also providing a Suppliers Forum at this meeting. This part of the meeting is a platform for SystemC EDA vendors to present technical views of their methodologies, tools, and libraries. If you are interested, please send a description of the demonstration until August 31st, 2010 to axel.braun@informatik.uni-tuebingen.de.

We are looking forward to your submissions!

With best regards,
Axel Braun, Wolfgang Rosenstiel

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The 22. European SystemC Users Group Meeting is supported by

ARM, Cadence, CoWare, Synopsys,
Mentor Graphics, Forte, OSCI, and Virtutech
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Facing challenges in ensuring the quality of your designs?
Please attend the 15th IEEE International High Level Design Validation and Test Workshop (HLDVT), co-located with DAC, June 11-12, 2010.

http://www.hldvt.com/10/

HLDVT 2010 advances research in validation, verification and test methodologies for integrated circuits and systems. The workshop focuses on addressing the current bottlenecks in validation and test of complex and heterogeneous systems by both employing high-level specifications (such as register transfer level, behavioral and system-level models) and developing associated tools, techniques and methodologies to enable drastic reduction in overall design, validation and test effort. The workshop provides a forum for leaders in both industry and academia to advance the means for validating, debugging, synthesizing, and testing complex systems in a way that opens new avenues to overcome current validation and test challenges.

This year, HLDVT provides rich program with five regular sessions, five special sessions, one tutorial, one panel and one keynote speech. There are several areas of focus. First, there is a session on firmware validation and a session on hardware-dependent software, to highlight the importance of embedded software. A session and a panel will be devoted to multi-clock systems and clock domain crossing verification, deployed in a variety of scenarios. One session will be devoted to transaction-level modeling, and another one will deal with high-level arithmetic circuit descriptions to obtain more from the circuits. Industry leaders in Electronic System Level (ESL) design will bring forward their perspectives on verification challenges at ESL, and a variety of papers will deal with formal verification advances, constraint solving, coverage and verification accelerators and emulators.

The complete program is available at http://www.hldvt.com/10/program.pdf

Further information including registration details are available at the HLDVT webpage http://www.hldvt.com/10. Please do not hesitate to contact us (prabhat@cise.ufl.edu or zeljko.zilic@mcgill.ca) if you have additional questions.

European SystemC User Group (ESCUG) Meeting DATE 2010

WHO: The Open SystemC Initiative (OSCI), an independent, non-profit organization dedicated to supporting and advancing SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced the annual European SystemC User Group (ESCUG) meeting. Co-located with the Design, Automation & Test in Europe (DATE) Conference, the event is free to industry professionals and the media. In addition, a half-day SystemC AMS tutorial will be conducted for DATE attendees.

WHAT/WHEN: Tutorial: “Application of the SystemC AMS Standard,” will take place Monday, March 8, 09:30 – 13:00. The annual ESCUG meeting will take place Tuesday, March 9, 18:30 – 21:30.

ESCUG AGENDA: The evening will feature an OSCI overview from President Mike Meredith, detailing results from individual OSCI Working Groups, including AMS, Synthesis, TLM-2.0, and CCI, and a special panel exploring 10 years of SystemC progress. In addition, technical luminaries from industry and academia will deliver papers describing advances in SystemC-based ESL design, modeling and interoperability for SoC and AMS Applications. For more information: www.systemc.org/news/events/.
WHERE: The SystemC AMS Tutorial, featuring noted speakers from the OSCI AMS Working Group, will be held in conjunction with DATE 2010 at the International Congress Centre, Konferenz 4. Advance registration for DATE tutorials is required. The ESCUG event will be held in Konferenz 2 at the Congress Centre. For additional information and to register, visit www.systemc.org/news/events/.

IP-ESC FRANCE: REGISTER NOW

Don't miss the opportunity to attend a unique three day event --held in Grenoble on 1 - 3 December. This event will cover all you need to know from IP to SoC to Embedded Systems.

Why Attend IP-ESC France?

IP–ESC 2009 addresses a continuous technical spectrum (from IP to SoC to Embedded System)
Industry gurus and world reknown speakers leading the conference educational sessions.
Expo Floor features industry heavy weights in the IP and embedded market.
3 days of education, product announcements, demonstations and networking.

You can view the program online now!

There are no excuses...if you are reading this email, ESC applies directly to you. Join the embedded community as we celebrate our annual ESC France event this December.

ESC FRANCE PANELS INCLUDE:

"IP Reuse vs. IP Leverage: What's the difference, and what are the issues?"
"Low volume designs that don't Always Stay That Way: Silicon industry solutions From Fabless chips to FPGAs"
"The evolution of semiconductor business models: is the fabless dead or alive and kicking?"
"Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?"
"Design and Reuse -The impossible dream?"
"Transactors: where the virtual world meets the implementation world"
"System Level IP: Challenges and Issues"
"Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?"
"From Processors to FPGAs to SoCs ? What are the best solutions to program algorithms onto hardware?"
"Silicon IP, Verification IP, Software Drivers, and design kits for a total IP solution"
"R&D in Europe teams up to master future system design"

Use discount code ESCFRANCE for ADVANCED DISCOUNT pricing. You save by registering now!

DATE 2010: Conference and Exhibition: March 8-12, 2010
Dresden, Germany

Scope of the Event

The 13th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community. Special space will also be allocated for EU-funded projects to show their results.

Structure of the Event

The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia and automotive systems. Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics.

Special Days in the programme will focus on two areas bringing new challenges to the system design community:
Nanoelectronics: Nanotechnology will permeate industrial products in the years to come, and will be present ubiquitously in various forms and means. In particular nanoelectronic circuits will exploit new materials (like carbon) to produce smaller and faster transistors, as well as integrated sensors with direct electronic coupling to the environment. The special day will address new nanotechnologies, their integration into electronic systems, and the EDA tools and methods for nanoelectronics.

Cool Electronic Systems: The search for low-power/energy systems is a cross-cutting issue that affects electronic systems designs in many ways, from circuits to architectures, from communication structures to software. The trend toward energy-conscious (green) system design affects products of various kinds, from the home to the office, from telephone/communications to embedded computing. This special day will address new methods and tools for circuit and system design at the frontier of minimum power/energy operation.
On the first day of the DATE event, half- and full-day in-depth technical tutorials are given by leading experts in their respective fields. The tutorials are well suited for researchers, tool developers and system designers.
Friday Workshops concentrate on specialised and novel topics.

The Exhibition

The conference is complemented by a large exhibition and unique networking opportunity for vendors of tools and services for hardware and embedded software for the design, development and test of Systems-on-Chip, IPs, Embedded Systems, ASICs, FPGAs and PCBs including a broad range of design reuse technologies and services.
To inform attendees on commercial and design related topics, there will be a full programme in the Exhibition Theatre which will combine presentations by exhibiting companies and selected conference special sessions.

IEEE International High Level Design Validation and Test Workshop 2009
November 4-6, 2009

IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level. The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, synthesizing, and testing designs specified using high level descriptions, in an effort to address high level design, validation, and test issues concurrently.