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Why use a virtual prototype when you have an FPGA?

 

This is a question that was posed in the "EDA-ESL and More" webcast today. Jason Andrews of Cadence offered these reasons: Virtual prototypes offer better controllability and visibility and they do not have intrusive debug.

He offered nothing in defense of FPGAs.

What do you think?
Discussion started by Brian Bailey , on 14 October 01:41 PM
Replies
Juergen Jaeger, 2009-10-22 16:19:25
Juergen Jaeger
Well, what I think is that both methodologies have their unique advantages and disadvantages, and in fact complement each other nicely.
Virtual prototypes enable pre-RTL (not just pre-silicon) software development and system exploration. However, they lack the "sense of reality" and fidelity that a FPGA prototype brings. So once, RTL becomes available the transition to a Rapid Prototype makes sense.
There are also additional considerations:
- for some parts of the design there may not be a virtual model available
- legacy RTL code exists
- IP is only available as RTL
All of that makes a hybrid of virtual prototype and rapid prototype, not only desirable, but the only possible solution.

In summary, dependent on the circumstances having both is nice, and if you can have one only, then go with the FPGA prototype!
 

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