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        <title><![CDATA[TB-Blog - TechBites]]></title>
        <description><![CDATA[TechBites - The Science and Technology Collaborative Community]]></description>
        <link>http://www.techbites.com/</link>
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                <guid isPermaLink="false">2264-660</guid>
	            <title><![CDATA[Videos show xMAX being put to the test: Marc Dannenberg Crazy cyber bully]]></title>
	            <link>/201003052264/myblog/blog/z0007-videos-show-xmax-being-put-to-the-test.html</link>
	            <description><![CDATA[
	            	            Marc Dannenberg Crazy cyber bully http://www.youtube.com/watch?v=5Vas1u2-0Eo	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 06 Dec 2011 18:07:25 -0600</pubDate>
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                <guid isPermaLink="false">1249-657</guid>
	            <title><![CDATA[Join My Green Energy Mafia!  Can Social Gaming Teach Us About a Sustainable Future?: Energy Literacy]]></title>
	            <link>/200911241249/myblog/blog/z001d-join-my-green-energy-mafia-can-social-gaming-teach-us-about-a-sustainable-future.html</link>
	            <description><![CDATA[
	            	            Thank you for sharing "Energy Literacy 101." It was a real eye opener.

http://www.edenpuresale.com	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 30 May 2011 21:50:03 -0500</pubDate>
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                <guid isPermaLink="false">3208-656</guid>
	            <title><![CDATA[Brian Bailey disagrees with the experts on IP integration: It's the same ... but worse]]></title>
	            <link>/201012173208/myblog/blog/z000d-brian-bailey-disagrees-with-the-experts-on-ip-integration.html</link>
	            <description><![CDATA[
	            	            Brian, I loved your piece on obstacles to ESL adoption from 3/30 on your new personal blog site.  It's worthwhile to post here on TechBites!

http://www.brianbailey.us/blog/?p=111

Interesting that you bring up the term 'pain point' because from my past experience as an EDA customer, changes closer to product release, especially tape-out (and silicon re-spin, apparently 2/3rds of the time!) cause enough pain for company management to offer up their treasure.  But that's an unsustainable model as systems become more complex, as you pointed out that past problems were not complex enough!  We have been able to get away with software patches and netlist tweeks.  Not for much longer ...	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sun, 03 Apr 2011 16:27:44 -0500</pubDate>
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                <guid isPermaLink="false">2773-655</guid>
	            <title><![CDATA[Cool Beans: NASA says that Voyager 2 is back online: Voyager 1]]></title>
	            <link>/201006042773/myblog/blog/z0002-cool-beans-nasa-says-that-voyager-2-is-back-online.html</link>
	            <description><![CDATA[
	            	            Voyager one, a nuclear powered space probe launched by NASA in 1977, is approaching the boundary of the solar system. I found this here: Voyager 1 nears edge of solar system after 33 years in space Voyager one has spent the last thirty-three years on a mission known as the “Grand Tour” which has taken it to Jupiter, Saturn and far beyond. Voyager one breaks the bonds of the solar system with an offering called the  Voyager Golden Record on board. The Voyager Golden record is a presentation of noises and pictures that gives intelligent existence the probe may encounter an idea of where it came from. 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 17 Dec 2010 05:07:27 -0600</pubDate>
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                <guid isPermaLink="false">3188-654</guid>
	            <title><![CDATA[Commentary: Big Brother is watching your driving habits: "Active Safety" vs Driver Reflexes]]></title>
	            <link>/201012023188/myblog/blog/z000e-commentary-big-brother-is-watching-your-driving-habits.html</link>
	            <description><![CDATA[
	            	            Also in the Driver Safety arena is lots of talk about automatic brakes.

I once almost had a accident on Interstate 80, in a construction zone.

Somehow a station-wagon that was over packed, pulled from between some construction equipment, in front of me.

This driver could not see out any window but right in front of him, and he was pulling *across* the interstate traffic, not going with the flow. He could not see out the passenger window, that was facing me.

He shot out from between the construction equipment about twenty feet in front of me, while I was doing 45 MPH, remember it was a construction zone.

The correct solutions to the problem was to floor the gas, so that I could get in front of him while there was still space, and get off on the right hand berm of the road.

Any "Active" braking system that thought it knew better would have caused the accident, not prevent it in this case.

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 15 Dec 2010 00:20:59 -0600</pubDate>
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	            <title><![CDATA[The Great Chicken Nugget Cake Caper - Adventures in Stealth Cuisine : Really takes the biscuit !]]></title>
	            <link>/201011193170/myblog/blog/z001f-the-great-chicken-nugget-cake-caper-adventures-in-stealth-cuisine.html</link>
	            <description><![CDATA[
	            	            Really inspirational. As a satisfactory day-to-day cook, keeping my working wife and our children alive, I just wish I could do something like this. Alas, pastry crumbles in my hands like the dust from a thrice-robbed tomb, or, more usually, turns into something that would handily fill that nasty crack in the wall. My wife, however, as well as being bright enough to earn money, and thus really keep us alive, is also a serious cook (weekends and when visitors come), and has a great line in "cake-men/-women" for the children's birthdays. They have come as witches, flamenco dancers, pirates and many others, but this is a whole new field of enterprise, and I will pass on these ideas for her to steal and elaborate on. Thanks a heap, and I will try to get her basic recipe to pass on to you. Belated happy birthday to Anwyn.

Andrew D-J	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 14 Dec 2010 22:47:54 -0600</pubDate>
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                <guid isPermaLink="false">3154-652</guid>
	            <title><![CDATA[Forgive me for tooting: Forgive me for tooting also.....]]></title>
	            <link>/201011093154/myblog/blog/z000e-forgive-me-for-tooting.html</link>
	            <description><![CDATA[
	            	             

Howard Martin
President 
Zocalo Tech, Inc.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 25 Nov 2010 21:49:10 -0600</pubDate>
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                <guid isPermaLink="false">2414-649</guid>
	            <title><![CDATA[Is 3DTV An Experiment?: 3D proponents lie like rugs]]></title>
	            <link>/201003242414/myblog/blog/z000a-is-3dtv-an-experiment.html</link>
	            <description><![CDATA[
	            	            There is a fundamental problem with ALL 3D technologies - they cause eyestrain for a significant percentage of viewers and actually make a few sick to their stomachs.

Here's why. You judge depth because as things get closer, your eyes have to cross to focus on them. So various 3D technologies use some mechanism to present slightly displaced images for each eye.

But in addition to crossing, your eyes simultaneously change focus as things get closer. But with ANY 3D technology, the images obviously can't actually get closer because they are right there on the screen all the time (duh!). So some viewers' eyes swim back and forth, focusing first on the screen and then attempting to focus closer and so on and so on.

This has been know since the first 3D movies came out in the 1950s and today's 3D proponents have been lying like rugs, saying advanced technology has overcome this "early" problem. Yeah, right. They re-engineered the Mk I Human Eyeball.

Chuck Small	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 22 Nov 2010 12:14:55 -0600</pubDate>
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                <guid isPermaLink="false">3136-646</guid>
	            <title><![CDATA[Is Intel acknowledging the future?: Time]]></title>
	            <link>/201011013136/myblog/blog/z0023-is-intel-acknowledging-the-future.html</link>
	            <description><![CDATA[
	            	            What is interesting about Achronix's technology is that it is based on asynchronous circuit design (some or all, I'm not entirely sure).  So Intel's fab may also be taking on additional challenge, courtesy of Achronix, and may eventually be better off in the long run from what they learn.

Also, regarding 'on shore' silicon, where are Actel's rad-hard components made?  (I don't know, I'd love to get an answer!)	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 02 Nov 2010 05:08:03 -0500</pubDate>
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                <guid isPermaLink="false">3119-645</guid>
	            <title><![CDATA[This one appears not to have an ARM or a leg?: ST responds]]></title>
	            <link>/201010213119/myblog/blog/z0023-this-one-appears-not-to-have-an-arm-or-a-leg.html</link>
	            <description><![CDATA[
	            	            The omission of details regarding the STM32 having an ARM core was most likely unintentional. We've announced related, compatible families for more than three years now beginning with licensing the core in October 2006 (http://www.st.com/stonline/stappl/cms/press/news/year2006/t2077.htm) and the first family of products in June 2007 (http://www.st.com/stonline/stappl/cms/press/news/year2007/p2184.htm), to an announcement at virtually every ESC thereafter.


As our web site (http://www.st.com/mcu/inchtml-pages-stm32_platform.html) and literature state, the STM32 family of 32-bit Flash Microcontrollers is based on the breakthrough ARM Cortex™-M3 core - a core specifically developed for embedded applications. The STM32 family benefits from the Cortex-M3 architectural enhancements including the Thumb-2 instruction set to deliver improved performance with better code density, significantly faster response to interrupts, all combined with industry leading power consumption. 


Compatibility of pin-assignments, peripherals and software across all STM32 devices is a core technical feature throughout this family of microcontrollers. 


All of the STM32 MCUs share the same tools and libraries, which are available from both ST and third-party suppliers (Keil/ARM, IAR, Raisonance, Atollic, Hitex) (http://www.st.com/mcu/inchtml-pages-stm32_tools.html). 

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 25 Oct 2010 16:40:36 -0500</pubDate>
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                <guid isPermaLink="false">2925-644</guid>
	            <title><![CDATA[Non-Cool Beans: Hackers in our hardware?: Helpless ???]]></title>
	            <link>/201008042925/myblog/blog/z000c-non-cool-beans-hackers-in-our-hardware.html</link>
	            <description><![CDATA[
	            	            (The following text is more of an augment than a review!)

Well clearly, the (well-written) article in 'Scientific American' is an example of the Principle of Equivalence of Hardware and Software - everything that can be done in software can be done in hardware too, and vice versa.

This could have dire consequences - imagine the processor company XYZ designing desktop chips that secretly record certain information, or mobile phones that could transmit sensitive data, or even speech segments to someone without the user noticing.

This technique COULD be used by military/intelligence agencies as a means of 'phone tapping' or 'wire tapping'. The mobile device (in the future) would have a speech recognition block that could detect 'odd' words (no example needed here!), and then transmit the necessary data to the concerned department.

Our lives are too much dependent on electronic instruments. Yet, we don't have any backup or alternate. Stephen Hawking, in the documentary 'Master of the Universe' commented that we should not put all eggs in one basket and should colonize other places in the solar system as well. Its time we think the same for our gadgets as well.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 30 Sep 2010 05:06:23 -0500</pubDate>
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                <guid isPermaLink="false">2998-643</guid>
	            <title><![CDATA[VDC says virtual prototypes may not be delivering: Did they measure any other benefits?]]></title>
	            <link>/201009072998/myblog/blog/z0019-vdc-says-virtual-prototypes-may-not-be-delivering.html</link>
	            <description><![CDATA[
	            	            The increase in usage (9% --> 15%) speaks volumes.  The tools are not hard to use (for the embedded developer handed a platform), so what holds up faster growth?  The availability of models!

I agree that virtual prototypes are helping us keep pace with increasing technology.  In addition I have the opinion that we do ourselves a disservice when we keep harping on the primary benefit of pre-silicon emulation and schedule saving without giving similar words to the quality improvements in the embedded system (warning messages), deterministic behavior, control-ability, fault injection, ability to pause/resume the stimuli and actuators, deep inspection of the system and regression capabilities.

Now for the shameful plug:

"How to make virtual prototyping better than designing with hardware" by Everett Lumpkin and Casey Alford

Part 1: http://www.embedded-systems.com/design/225701094
Part 2: http://www.embedded-systems.com/design/225701109	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 08 Sep 2010 01:09:53 -0500</pubDate>
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                <guid isPermaLink="false">2992-642</guid>
	            <title><![CDATA[Experts have catfight at the table: good post]]></title>
	            <link>/201009032992/myblog/blog/z000e-experts-have-catfight-at-the-table.html</link>
	            <description><![CDATA[
	            	            Brian, good post. Amazing how in one short post a person can see so many things that make h/w development such a challenge, and few of them are technical. Such a wild variance in perspective, opinion, experience, location, goals, motivation, specialty, etc, etc, etc... and that's just a small group of 4/5 people!

Last sentence is very strong and that conversation demonstrates it so obviously applies to more than just outsourcing... "many companies have found ways to make it work and in my observations the ones that work all had very good communications at the heart of it". Well said.

neil	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 03 Sep 2010 17:18:12 -0500</pubDate>
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                <guid isPermaLink="false">1530-641</guid>
	            <title><![CDATA[SystemC and Transaction-Level Modeling (TLM): chjchj]]></title>
	            <link>/200912211530/myblog/blog/z000c-systemc-and-transaction-level-modeling-tlm.html</link>
	            <description><![CDATA[
	            	            že jsem dostal http://www.uggbootsladens.com/kids-boots.html  sedadlo na křídle v přízemí, a křídlo  http://www.uggbootsladens.com/kids-boots.html je jednoduše obrovské a  http://www.uggbootsladens.com/kids-boots.html brání ve výhledu, a zejména proto, že jsme celou dobu letěli v noci.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 31 Aug 2010 01:50:58 -0500</pubDate>
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                <guid isPermaLink="false">2974-640</guid>
	            <title><![CDATA[What do you get if you cross Falcon with EDA 360?: Let us know how you go making something!]]></title>
	            <link>/201008232974/myblog/blog/z000d-what-do-you-get-if-you-cross-falcon-with-eda-360.html</link>
	            <description><![CDATA[
	            	            Hi Brian,

In the interest of full disclosure - I am immersed in the Altium "coolaid" - yet I had no idea you were going to post about Altium things. So thanks for that :-)

I am curious what is not working for you on Windows 7 though - is it the version of FPGA vendor tools you were using for Place and Route?

Altium Designer's current release has no qualms on Windows 7 - I'm running it on two Win 7 machines no problems (although, Windows 7 does impose some security features on the reference design folder for 'Summer '09' - R10 we will be putting those reference designs in the public user folder, which is really where they should have been all along).

Let me know how you get on tinkering with that NB3000. It can be a lot of fun - as long as you have an open mind about methodology.

Ben.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 25 Aug 2010 00:28:34 -0500</pubDate>
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                <guid isPermaLink="false">2974-639</guid>
	            <title><![CDATA[What do you get if you cross Falcon with EDA 360?: Have you used the Altium system?]]></title>
	            <link>/201008232974/myblog/blog/z000d-what-do-you-get-if-you-cross-falcon-with-eda-360.html</link>
	            <description><![CDATA[
	            	            Brian,
I mostly agree with you about Altium and have played with their system, http://www.chipdesignmag.com/payne/2010/03/27/altium-nanoboard-fpga-design-made-simple/ 

Did you ever receive their system and put it through the paces?

Just curious.

Daniel	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 24 Aug 2010 04:50:03 -0500</pubDate>
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                <guid isPermaLink="false">2972-638</guid>
	            <title><![CDATA[Webinar: Ultra Tiny Linux OS for SmartFusion Mixed-Signal FPGAs: RoweBots other info, ]]></title>
	            <link>/201008182972/myblog/blog/z0002-webinar-ultra-tiny-linux-os-for-smartfusion-mixed-signal-fpgas.html</link>
	            <description><![CDATA[
	            	            RoweBots already has a small linux footprint for some of the Renesas MCU's.  Combining the two would put quite a bit of computing power on the board.  The combination of an RTOS on the MCU and integrated with an RTOS FPGA could prove to be interesting.  	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 20 Aug 2010 12:26:00 -0500</pubDate>
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                <guid isPermaLink="false">2928-637</guid>
	            <title><![CDATA[Win a free Actel SmartFusion mixed-signal FPGA evaluation kit!: The document has been updated on actel.com]]></title>
	            <link>/201008052928/myblog/blog/z0002-win-a-free-actel-smartfusion-mixed-signal-fpga-evaluation-kit.html</link>
	            <description><![CDATA[
	            	            Hi, Actel has updated the document and it is now live on actel.com. You can find the document at: http://www.actel.com/documents/SmartFusion_LiberoSoftConsole_POTlevel_tutorial_UG.pdf

The answers to each unresolved issue appear below:

In # 2 on page 16 “Select the four GPIO pins, right-click, and select Promote to Top Level”. This may have been automatic in Libero 9, because I did not have to do this step.
[Actel] Yes, this was automated on Libero IDE v9.0 in SP1 and the tutorial has been updated to reflect that.

In step 6, page 27. I set the jumpers as described. But I did not see any other jumper settings later.
[Actel] See my response to last comment below.

Step 7, page 30. Windows 7 does not have HyperTerm. I used PuTTY. It seemed to work OK.
[Actel] The updated tutorial provides a way to use PuTTY and TeraTerm for Windows 7 users.

Page 36-39. I tried copying the code from the tutorial, but it did not compile. I got the code off the Actel webpage, and it did compile.
[Actel] All steps were retested when updating the tutorial and we found no issues at all. Could be a copy/paste issue (indentation might have changed while copy/paste).

Configuring debug target, page 42. Following the directions, setup a debug perspective on page 43. IT DOES NOT RUN. I opened a case, where I was asked what the jumpers were I had set. There were no changes mentioned in the document since step 6, above. I plain ran out of time to continue.
[Actel] The jumper settings for program and debug are the same. The jumper settings described in step 6 work for debug, which describes the 4 jumpers that must be set.

Let us know if you still have any issues, we welcome your feedback.
You can contact us on Twitter: @Actelcorp, Facebook: http://www.facebook.com/ActelCorp or by email: social.media@actel.com).
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 06 Aug 2010 21:00:10 -0500</pubDate>
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                <guid isPermaLink="false">2926-636</guid>
	            <title><![CDATA[March 1966: Use Bluespec !]]></title>
	            <link>/201008052926/myblog/blog/z000d-march-1966.html</link>
	            <description><![CDATA[
	            	            Read the title ...	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 06 Aug 2010 17:58:23 -0500</pubDate>
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                <guid isPermaLink="false">2927-635</guid>
	            <title><![CDATA[Verilog 'full_case' and 'parallel_case' synthesis directives: prallel case]]></title>
	            <link>/201008052927/myblog/blog/z000c-verilog-fullcase-and-parallelcase-synthesis-directives.html</link>
	            <description><![CDATA[
	            	            how parallel case remove priority encoder from design?? do u have any example that prove this thing?	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 06 Aug 2010 08:22:45 -0500</pubDate>
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                <guid isPermaLink="false">2927-634</guid>
	            <title><![CDATA[Verilog 'full_case' and 'parallel_case' synthesis directives: Well, that's a bit of a downer :-)]]></title>
	            <link>/201008052927/myblog/blog/z000c-verilog-fullcase-and-parallelcase-synthesis-directives.html</link>
	            <description><![CDATA[
	            	            Hi Ravi -- you've taken the wind out of my sails (as they say) -- I was convinced that this paper would leave you with a big smile on your face and have you dancing in the streets.

Well, let's ask the other folks at TechBites to chip in - maybe post their response in the form of an article. Otherwise, if anyone cares to send a detailed answer to me, I'll post it in the form of a blog...	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 05 Aug 2010 20:09:44 -0500</pubDate>
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                <guid isPermaLink="false">2927-633</guid>
	            <title><![CDATA[Verilog 'full_case' and 'parallel_case' synthesis directives: full parallel case]]></title>
	            <link>/201008052927/myblog/blog/z000c-verilog-fullcase-and-parallelcase-synthesis-directives.html</link>
	            <description><![CDATA[
	            	            Hi Max...I have already read this pdf file. but i want any practical verilog code that show difference between full case and parallel case. I have run this pdf code on altera tool but getting same Logic element inside hardware. This question is asked by interviewer and they want ans with example. 

See Below questions:

What is difference between full case and parallel case?
what is advantage over each other and which is best choice to used in design?
when to use parallel case and when to use full case?

i need any experience person answer on above questions.

Thanks in Advance.... 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 05 Aug 2010 14:02:44 -0500</pubDate>
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                <guid isPermaLink="false">2922-632</guid>
	            <title><![CDATA[Specifying concurrency: It's definitely all in the tradeoffs...]]></title>
	            <link>/201008032922/myblog/blog/z000d-specifying-concurrency.html</link>
	            <description><![CDATA[
	            	            Thoughtful piece Brian.  If you're writing a functional model, C/C++/SystemC may be the right tool for you.  And, if C-based synthesis delivers sufficient results (area/timing/throughput/...) in an acceptable timeframe to meet your needs, C/C++/SystemC-based design may be the right approach for you.  But, there's the rub...  do your requirements allow you to live with the tradeoffs and unpredictability of C-based synthesis tools, in the many areas where they cannot discern enough concurrency or express the best architecture?

Good hardware is about good architecture.  And, we think modelers, architects, verification engineers and designers are much better at hardware architecture than tools are.  High-level architectures should be left to these engineers, not to tools, so hardware language needs to express it.  For system interconnects, complex controllers, and many of today's algorithms (e.g. those with data-dependent operations, with complex feedback loops, with multiple interconnected blocks, or that may benefit from tight incorporation with memory or DMA subsystem considerations, etc.), concurrency is not only complex but much of the problem.  And, it's in just this area that SystemC offers little over RTL.

At the HLS panel at DAC, the argument from the C folks was that using C/C++/SystemC was "practical", because so many knew it.  But it's only "practical" when it meets your requirements.  Why do so many use Mathworks and not C or some C-based language for expressing math?  Certainly so many more know C...

If you want a high-level of abstraction across system interconnects, controllers, as well as complex algorithms, and a high-level abstraction that is uniformly synthesizable, then we believe you have to address concurrency.  It's fundamental to hardware.  Bluespec's concurrency enables synthesizable modeling, test benches, transactors and implementations, for all types of digital designs at a high-level of abstraction.  And, in stark contrast to C/C++/SystemC, Bluespec keeps engineers 100% in control of architecture.


Here are a few useful background references (not about Bluespec, but about C-based synthesis and concurrency):

*  "Lessons and Experiences with High-Level Synthesis" in the July/August 2009 issue of IEEE Design & Test Magazine (and an interesting follow up viewing is http://www2.dac.com/videos+from+dac+user+track+videos.aspx for conclusions about where C-based synthesis may add value, given the conclusions reached in the paper (specifically, the video entitled "Advances in System-Level Design and Synthesis")

On the issues with threads, which are fundamental to SystemC's concurrency model (note that these issues transcend programmers familiarity with parallel programming):

*  Tim Bray's (co-inventor of XML and Google Android developer) recent comments on threads (link of my blog entry: http://chipsandbs.blogspot.com/2010/07/lessons-from-software-space.html)
*  Prof Ed Lee's (of Berkeley) paper on "The Problem with Threads" at www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.pdf	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 05 Aug 2010 02:57:53 -0500</pubDate>
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                <guid isPermaLink="false">2906-631</guid>
	            <title><![CDATA[Where should a young engineer go to learn about verification?: Salemi's book]]></title>
	            <link>/201007282906/myblog/blog/z000c-where-should-a-young-engineer-go-to-learn-about-verification.html</link>
	            <description><![CDATA[
	            	            Hi all,

I have started with Ray Salemi's "FPGA Simulation" book. A geat one to get started and get a grasp of what is needed and what is available. Also, www.verificationacademy.net is a good resource on introductory material from Mentor. And of course: practice!

JaaC	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 03 Aug 2010 10:22:16 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2910-630</guid>
	            <title><![CDATA[PCB 101 – New series of articles: pcb101   any ideas  ]]></title>
	            <link>/201007292910/myblog/blog/z000c-pcb-101-new-series-of-articles.html</link>
	            <description><![CDATA[
	            	            HI   I am Robert Tarzwell  , I write the pcb101 column,  thanks for the good review, question is  what do people want to read about , if you have any ideas for pcb101 stories  let me know , the email is on the pcb007 web site   bob@dmrpcb.com,  we are just getting to the printer with the first pcb101 book  a handbook on pcb manufacturing , 100 pages  lots of interesting  photos .  

Robert Tarzwell 
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 02 Aug 2010 18:57:10 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2914-629</guid>
	            <title><![CDATA[Funny Beans: Maintaining *To-Do* lists (I'm afraid I told a lie): Guilty]]></title>
	            <link>/201007302914/myblog/blog/z0002-funny-beans-maintaining-to-do-lists-im-afraid-i-told-a-lie.html</link>
	            <description><![CDATA[
	            	            ...though I think it's useful for tracking purposes...  :>)  Errr...  ahem...

BTW - I'm a big fan of www.rememberthemilk.com (primarily for their website interface; I have the iPhone app but use it infrequently).	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 02 Aug 2010 17:45:59 -0500</pubDate>
            </item>
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                <guid isPermaLink="false">2906-628</guid>
	            <title><![CDATA[Where should a young engineer go to learn about verification?: A mandatory First Step]]></title>
	            <link>/201007282906/myblog/blog/z000c-where-should-a-young-engineer-go-to-learn-about-verification.html</link>
	            <description><![CDATA[
	            	            First off, there is no one right way to do verification. Every design, every group, every company has different priorities, amount they can spend and a different desired quality. If you are designing a childs toy, there are very different verification requirements compared to the verification of a implantable medical device. Intel has a different quality standard compared to most companies because of the impact on their image of errors that creep out. While I hate to call verification an "art", there are aspects of it that are, although careful planning and implementation make it more of a well thought out strategy.

To make the right trade-offs, you have to really understand the basics and I believe the best book for that is an old one now, but still relevant. Writing Testbenches by Janick Bergeron. There are several editions of this available and the best one is the one about SystemVerilog as this creates a more modern and extensible verification framework than earlier editions.

After that, it is probably best to look as some of the verification frameworks, such as OVM or UVM. These too contain lots of information about how to structure the testbench correctly. Then there are lots of books about various languages that may be of use once you have decided on the basic techniques. After that - I think you will know what you need to write some good testbenches. The rest is just practice.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 02 Aug 2010 17:22:08 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2906-627</guid>
	            <title><![CDATA[Where should a young engineer go to learn about verification?: Learning Verif in real sense]]></title>
	            <link>/201007282906/myblog/blog/z000c-where-should-a-young-engineer-go-to-learn-about-verification.html</link>
	            <description><![CDATA[
	            	            Ravi,
  Maybe you are looking for an inhouse "Verification architect" to have frequent discussions. But things like parallel-to-serial block are far easier than the need for such an expert - maybe that was just "an example" you quoted. 

In terms to nitty gritties of doing from scratch verification with all modern technologies/methodologies and languages, take a look at UVM/OVM/VMM. Tons of examples are around on the net @ www.uvmworld.org (SoC ref kit), www.ovmworld.org, www.vmmcentral.org

Of-course you need a capable simulator to master these - maybe you have access to it already. If not consider talking to us via www.cvcblr.com/trainings - we do this as a professional service/training with duration being 2 weeks, 4 weeks etc. 

Good Luck
Srini
www.cvcblr.com/blog 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sat, 31 Jul 2010 02:40:59 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2906-626</guid>
	            <title><![CDATA[Where should a young engineer go to learn about verification?: testbench]]></title>
	            <link>/201007282906/myblog/blog/z000c-where-should-a-young-engineer-go-to-learn-about-verification.html</link>
	            <description><![CDATA[
	            	            Hi Gopi,

I have read this site but i need some practical environment Example. 
How clock and Reset generation block is created(its not like as mention in site just create one initial block for clock and one initial block for reset)?
There are some consideration for generate generic clock and reset for synchronous and asynchronous systems.
 
If i have to verify one parallel to serial converter Block then what is step i have to follow for complete verification of this block?

Best Regards:

R@vi	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 30 Jul 2010 04:55:53 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2906-625</guid>
	            <title><![CDATA[Where should a young engineer go to learn about verification?: www.testbench.in]]></title>
	            <link>/201007282906/myblog/blog/z000c-where-should-a-young-engineer-go-to-learn-about-verification.html</link>
	            <description><![CDATA[
	            	            From School days Linear testbecnchs to Todays UVM 
are on www.testbench.in 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 29 Jul 2010 06:20:39 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2662-624</guid>
	            <title><![CDATA[Neat videos: Future dashboards—tomorrow's 'green' HMIs: Automotive XPrize about to be awarded]]></title>
	            <link>/201005032662/myblog/blog/z0013-neat-videos-future-dashboardstomorrows-green-hmis.html</link>
	            <description><![CDATA[
	            	            The Progressive Automotive X Prize has long been considered the “holy grail” of vehicle efficiency. This event is all about science. It has something to with environment and science technology. You will not need personal financing to put your vehicle into production if you win the XPrize because it is a $5 million award. 

I found this here: Automotive XPrize about to be awarded

Michigan is leading the way for the prize with two cars that have a shot at winning right now alone.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 27 Jul 2010 05:25:12 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2894-623</guid>
	            <title><![CDATA[New Book: TLM-Driven Design and Verification Methodology: TLM Book Preview]]></title>
	            <link>/201007212894/myblog/blog/z000d-new-book-tlm-driven-design-and-verification-methodology.html</link>
	            <description><![CDATA[
	            	            Brian,

Thanks for your help - a preview of the book can be seen at http://www.cadence.com/products/sd/Pages/tlm.aspx

Steve

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 21 Jul 2010 21:04:19 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2885-622</guid>
	            <title><![CDATA[Cool Beans: All the good ideas haven’t been taken (yet)!: The stair storage]]></title>
	            <link>/201007192885/myblog/blog/z0002-cool-beans-all-the-good-ideas-havent-been-taken-yet.html</link>
	            <description><![CDATA[
	            	            Those are from a Japanese house.  The first thing you do entering into a home in Japan is to remove your shoes, and use house slippers provided.  This idea is for upstairs living when the door is downstairs.  

Makes it a lot more space saving not having to place the shoe cabinet in the doorway. 
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 20 Jul 2010 14:07:01 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2869-620</guid>
	            <title><![CDATA[Cool Beans: Making my own PCB (or not): Usea Egale For the layout]]></title>
	            <link>/201007082869/myblog/blog/z0022-cool-beans-making-my-own-pcb-or-not.html</link>
	            <description><![CDATA[
	            	            For two layers designs, 10x10, it's free and very easy to use, a lots of librarys are available.
http://www.cadsoftusa.com/

And thsi is a colelction of useful libraries for Eagle:
http://www.opencircuits.com/SFE_Footprint_Library_Eagle

bye	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 14 Jul 2010 14:58:24 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2859-619</guid>
	            <title><![CDATA[Cool Beans: Prototype Steampunk Pseudo-Coal-Fired Furnace Works!: More power....]]></title>
	            <link>/201007072859/myblog/blog/z0002-cool-beans-prototype-steampunk-pseudo-coal-fired-furnace-works.html</link>
	            <description><![CDATA[
	            	            Max,

If pre-heat the anti-matter and increase the intermix ratio you may get that thing over warp 2.

It looks very cool... can't wait to see it completed.

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 07 Jul 2010 09:25:04 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2840-618</guid>
	            <title><![CDATA[Mentor Management tries to protect itself: EDA is in a funk, period]]></title>
	            <link>/201006282840/myblog/blog/z000e-mentor-management-tries-to-protect-itself.html</link>
	            <description><![CDATA[
	            	            Brian, while Synopsys has done best of the Big 3 EDA firms (thanks much to Design Compiler, and DesignWare), Jasper has done well amongst the small guys and Magillem achieved an IPO in late 2009 (the most under-reported story in EDA last year, where there is a VC slump along with fabless semi start-ups), the vast bulk of the EDA industry has not done well.  Even if Mentor Graphics had done as well, that would still be a sub-par performance by most measures of the software or semiconductor industries.

I'm actually looking at this from a contrarian standpoint: that Icahn is looking to extract value out of Mentor by upping their performance rather than making radical changes or slicing off and selling valuable pieces (for which buyers would be hard to find).  Much like the case of Marvel Comics, which triggered a rich buy-out by Disney and even revived a lawsuit by the heirs of Jack Kirby.

When you look at the Mentor Graphics portfolio of technologies, they are well-suited to tackle solutions at a higher level like Cadence has enunciated in their EDA360 agenda. 

Disclaimer: I once worked for Mentor Graphics, until over a year ago.  That's the past! :)
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 28 Jun 2010 23:01:35 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2819-617</guid>
	            <title><![CDATA[DAC attendance falling: I guess it just depends]]></title>
	            <link>/201006222819/myblog/blog/z000d-dac-attendance-falling.html</link>
	            <description><![CDATA[
	            	            I look at the same numbers and see them increasing year over year, at least for the free exhibit part. And at the same time just the pay for classes dropping... yet another sign of the economy, "Yes you can go to see what's new but we're not paying for any seminars."	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 28 Jun 2010 17:51:01 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2833-616</guid>
	            <title><![CDATA[Altera delivers single-chip FPGA solution for HD WDR surveillance cameras: Fast and easy with great dynamic enhancement]]></title>
	            <link>/201006242833/myblog/blog/z0002-altera-delivers-single-chip-fpga-solution-for-hd-wdr-surveillance-cameras.html</link>
	            <description><![CDATA[
	            	            An interesting development board that gives you a fast jumping off point but some of the claims are misleading. They drop every other of the 60 Hz frames to get to the 30 Hz and they demosaic from Bayer resolution HD images and then color space convert, process and encode the data so you really aren't even close to HD resolution. Plus, because they go from one color per pixel (Bayer) to YUV with more bits they're actually encoding lower resolution into more bits before transmitting. But it makes the backend tool just have to display standard video. If they wanted to get higher resolution data they could compress each color of the Bayer image then transmit it and post process on the display end and have more image data available. All that said, the wide dynamic range image enhancements are impressive (see the white paper figure 4).	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 28 Jun 2010 17:22:22 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2827-615</guid>
	            <title><![CDATA[Education is a two way problem: End of the Beginning]]></title>
	            <link>/201006242827/myblog/blog/z000d-education-is-a-two-way-problem.html</link>
	            <description><![CDATA[
	            	            Brian, I was part of the Platform Express program at Mentor Graphics from which IP-XACT was spawned out by their technology donation to the SPIRIT Consortium.  While I cannot comment on the actual status of that program (because, honestly, I do not know!  It is still being offered in a bundle as an IP solution with HDL Designer on MGC's website), one can go one step further and look at papers from past IP/IP-SOC conferences by NXP, who created NxBuilder as their own custom application layer extending the Platform Express base.  The takeaway is that a combined investment was needed by both the user and the EDA provider.  If only done by the latter, knowledge (i.e., education) would have to flow from the design community to the EDA developer if electronics firms expect a solution that comes right out of the box.  There are other successful EDA solutions for IP integration in SoC design that make use of IP-XACT, notably Magillem, Duolog, as well as Synopsys (CoreTools, DesignWare) and now Cadence (Open Integration Platform, mentioned in the EDA360 white paper).  But I cannot imagine that any adopter can expect a generic solution that works out of the box when their own SoC development flows have proprietary characteristics.  So there is some level of investment required by a user, an investment that was probably put into question (despite relevance to the core business) under financial pressures of the recent Great Recession. :(	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sat, 26 Jun 2010 06:16:47 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2834-614</guid>
	            <title><![CDATA[Cool Beans: Using Skype for screen sharing and other stuff: seriously useful thing]]></title>
	            <link>/201006242834/myblog/blog/z000c-cool-beans-using-skype-for-screen-sharing-and-other-stuff.html</link>
	            <description><![CDATA[
	            	            Skype that is, have been using it for a couple of years, at least 5 days a week on a global basis. 
And more to the point, for a paltry annual fee or two [less than 200$/annum] I get the following:-

1. unlimited calls to land lines practically anywhere in the world of use to me, and to mobiles where user pays incoming calls ie USA, HongKong etc

2. local direct dial numbers in both USA and the UK, so the great unwashed [no nerd genes] can just call me from whatever hand-set/mobile they like; particularly useful for ageing relatives and cheap-skate self-employed hacks that live in the 1st world

3. calls diverted to my mobile should I not answer at my computer, plus the ability to call from my mobile by just calling a local number and then dialling as in No1 above

4. an excellent answering service

It currently doesn't get any better, Vonage/Comcast/ATT and the like are just crazed fools in comparison.

the other Clive
ps: call quality is excellent when I'm not mucking about with my system, its connections and the like	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 25 Jun 2010 17:58:42 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2794-613</guid>
	            <title><![CDATA[Synfora bites the dust: Synphony]]></title>
	            <link>/201006102794/myblog/blog/z000d-synfora-bites-the-dust.html</link>
	            <description><![CDATA[
	            	            Thanks for the commentary, Brian!

Question: Do you or any of your readers have any insight on what happened with Synphony, why was it not more successful?

On the face of it, would seem like an important contribution and market....

best,
Holly	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 18 Jun 2010 15:47:40 -0500</pubDate>
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                <guid isPermaLink="false">2804-612</guid>
	            <title><![CDATA[False Anticipation?: Getting Back in the Saddle]]></title>
	            <link>/201006162804/myblog/blog/z000d-false-anticipation.html</link>
	            <description><![CDATA[
	            	            Brian, I've only seen a 2-3 enthusiastic tweets on DAC attendance, probably from the Exhibits Hall, while e-mail and Skype chats have been glummer.  Mind you, the latter is partly comprised of job seekers, while the former are people in the thick of it.  Yours is the first deviation from the two, that I have seen! :)

The tweetpics being posted show lots of empty seats at the Pavilion and stuff, but that's how I remembered it when I was an EDA customer (mid/late 90's, early 00's) as well as in the EDA industry afterward.

G	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 16 Jun 2010 18:33:34 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2775-611</guid>
	            <title><![CDATA[Brian Bailey’s must see list for DAC 2010: ESL to GDSII ECO flow]]></title>
	            <link>/201006072775/myblog/blog/z000e-brian-baileys-must-see-list-for-dac-2010.html</link>
	            <description><![CDATA[
	            	            Brian,

It is indeed very exciting to see ESL pick up momentum, and I'm sure we'll start seeing more capbilities and flows around ESL being developed. One very unique capability Cadence has is a complete ESL to GDSII ECO flow. As anyone who has designed a chip (either at ESL or RTL level) would know, almost all designs go through ECOs and they can be very time consuming. Using Cadence's ECO flow, one can automate the process of ECO implementation and save valuable time. We'll be showing this at DAC this year (booth 1334).

Yoon	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 11 Jun 2010 22:38:36 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2787-610</guid>
	            <title><![CDATA[Cool Beans: 5V, 30A power supplies for only $5: Happy Dance]]></title>
	            <link>/201006092787/myblog/blog/z0022-cool-beans-5v-30a-power-supplies-for-only-5.html</link>
	            <description><![CDATA[
	            	            Now if you have never seen Max’s happy dance  – It was modeled on the 3D Studio MAX animated Baby video that was the rage some 10 years ago. See if you can fine it on the net. It would be a great post.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 10 Jun 2010 13:14:51 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2775-609</guid>
	            <title><![CDATA[Brian Bailey’s must see list for DAC 2010: Cadence Best UVM demo at DAC]]></title>
	            <link>/201006072775/myblog/blog/z000e-brian-baileys-must-see-list-for-dac-2010.html</link>
	            <description><![CDATA[
	            	            Hi Brian,

Just in time for the UVM, Cadence is back to DAC in a much bigger way than the previous years.  For your readers, one thing I can highlight is the "Best UVM" demo in our Silicon Realization pod on the DAC floor in booth #1334.  We have a wide array of technology and solutions from building the UVM environment, to running it fast, to analyzing and debugging the results.  We'll even have something _new_, though I can't mention exactly what it is just yet.  You'll have to stay tuned for a few more days!

Hopefully your readers will be happy to see Cadence back at DAC in a strong way and will stop by to see the news on UVM and the other Cadence offerings.

=Adam Sherer, Cadence Verification Product Management Director	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 09 Jun 2010 21:47:46 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2774-608</guid>
	            <title><![CDATA[Calypto goes a little loopy and loses its memory: TLM verification]]></title>
	            <link>/201006072774/myblog/blog/z0000-calypto-goes-a-little-loopy-and-loses-its-memory.html</link>
	            <description><![CDATA[
	            	            Cadence has contributed to the recently announced TSMC ESL reference flow for verification which describes how to implement a simulation-based approach. We have also Collaborated extensively with Calypto to provide customers with a solution the adds SLEC to the ESL verification methodology, and enables the synthesis and SLEC processes to work well for the complex control and datapath IP designs that modern high level synthesis is applied to.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 09 Jun 2010 21:11:13 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2772-606</guid>
	            <title><![CDATA[YES! Mentor introduces Rad-Tolerant FPGA Synthesis!: Nice articule, looks like an excelent stuff to learn.]]></title>
	            <link>/201006032772/myblog/blog/z0002-yes-mentor-introduces-rad-tolerant-fpga-synthesis.html</link>
	            <description><![CDATA[
	            	            I never consider rad-rpotection in my designs, I didn't realize that rad could be very close to someone.Defnitly something I'm going to research about. I'll be waiting for your book.
Bye!	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 09 Jun 2010 06:00:31 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2775-605</guid>
	            <title><![CDATA[Brian Bailey’s must see list for DAC 2010: Can you please add something on Emulation/prototyping products?]]></title>
	            <link>/201006072775/myblog/blog/z000e-brian-baileys-must-see-list-for-dac-2010.html</link>
	            <description><![CDATA[
	            	            Hi Brian,
  Interesting coverage on ESL & brief one on Pre-Si Verification (if you allow, here is my list/round-up www.cvcblr.com/?p=170).

Can you please cover the likes of EVE, HAPS, GateRocket etc.

Regards
Srini
www.cvcblr.com/blog 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 07 Jun 2010 15:49:19 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2768-604</guid>
	            <title><![CDATA[Agnisys closes the loop on requirements: Thanks Brian!]]></title>
	            <link>/201006032768/myblog/blog/z000e-agnisys-closes-the-loop-on-requirements.html</link>
	            <description><![CDATA[
	            	            Thanks Brian for the writeup! Its nice to see bloggers and opinion makers like yourself who are independent and who don't just write up for a fee.

BTW, we are organizing a BoF at DAC to talk about Agile Verification Management. 

I've posted more details here :

http://www.techbites.com/groups/verification/view-discussion/agile-verification-management-bof-at-dac/

Care to join us?

Anupam
Agnisys, Inc.
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 03 Jun 2010 19:27:26 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2742-603</guid>
	            <title><![CDATA[Cool Beans: Noise-cancelling Bluetooth headset for my cell phone: Jawbone ICON]]></title>
	            <link>/201005212742/myblog/blog/z000c-cool-beans-noise-cancelling-bluetooth-headset-for-my-cell-phone.html</link>
	            <description><![CDATA[
	            	            For noise cancellation, Jawbone is another good option. I purchased the first version of Jawbone. 
Their latest ICON product line some great features:
http://www.jawbone.com/productsPageIconWhatsNew.aspx	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 03 Jun 2010 12:34:58 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2763-602</guid>
	            <title><![CDATA[There is VC funding for EDA startups: And there can be IPO's, too!]]></title>
	            <link>/201006022763/myblog/blog/z000d-there-is-vc-funding-for-eda-startups.html</link>
	            <description><![CDATA[
	            	            Brian, not only is there VC (or angel investor) funding out there ... somewhere ... IPO's are not entirely extinct.  Maybe it was due to the collapse of the EDA press but Magillem's IPO in late November 2009 was THE top missed story in our field ...
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 02 Jun 2010 23:08:12 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2757-601</guid>
	            <title><![CDATA[Is Synopsys getting ready to buy EVE?: Is Synopsys getting ready to buy EVE? ]]></title>
	            <link>/201006012757/myblog/blog/z000e-is-synopsys-getting-ready-to-buy-eve.html</link>
	            <description><![CDATA[
	            	            Brian,
The idea of hybrid of virtual platform and HW-assisted verification is not new. I have discussed the flow starting from virtual platforms with a hybrid of HW-assisted verification and eventually migration to emulation or FPGA-based prototyping several times in the last few years. Also, Cadence and its customers implemented this flow in the last few years.

1. Cadence introduced a combined solution of virtual platform and Palladium acceleration in 2004 -http://www.cdnusers.org/community/incisive/Itp_systemCbasedvirtualSoC.pdf
2. Cadence introduced a combined solution with Virtio and Palladium in 2006  
3. Cadence has created a native environment combining its SystemC simulator with Palladium
4.  Cadence introduced a combined solution with Palladium and Simics this year

Also, the idea of a hybrid platform combining TLM and HW acceleration is not new. Cadence announced its SCE-MI 1.0 in 2003/2004 and SCE-MI 2.0 in 2008/9. Cadence also delivered its support for SystemVerilog DPI and TLM 1.0 and TLM 2.0 in the last few of years.
Based on the latest announcement from Eve, the only news I see here is that Eve joined “the club” with their support of TLM 2.0 by implementing their own TLM 2.0 transactor. However they are still using their own proprietary interface ZEMI vs. the SCE-MI standards.

Ran Avinun
Cadence Design Systems
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 02 Jun 2010 06:40:44 -0500</pubDate>
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                <guid isPermaLink="false">2743-600</guid>
	            <title><![CDATA[Did you want a simulator with that FPGA?: Real Designers use simulators]]></title>
	            <link>/201005262743/myblog/blog/z000e-did-you-want-a-simulator-with-that-fpga.html</link>
	            <description><![CDATA[
	            	            Brian, you hit the nail on the head in terms of the evolution of verification for FPGA designers. With any FPGA bigger than 10-20K gates, I couldn't imagine not doing at least some level of simulation before programming the device for in-system testing, and having simulation available to help debug problems found during this testing. I'm glad to see Altium and Aldec helping to make it happen.

Tom A.
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 27 May 2010 22:06:06 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2737-599</guid>
	            <title><![CDATA[Hurray! ColdFire processor cores for Tabula's new ABAX FPGAs: Back to the Future]]></title>
	            <link>/201005202737/myblog/blog/z0002-hurray-coldfire-processor-cores-for-tabulas-new-abax-fpgas.html</link>
	            <description><![CDATA[
	            	            An out-of-the-box selection but it appears that Tabula is looking to attract users of micro-controllers familiar with 6800 and 68000 (i.e., ColdFire) architectures but looking for more in performance, etc. And there is legacy code reuse potential, too!	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 21 May 2010 01:09:08 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2732-598</guid>
	            <title><![CDATA[Verilog simulator available for the Mac: OS X is built on BSD Unix]]></title>
	            <link>/201005192732/myblog/blog/z000e-verilog-simulator-available-for-the-mac.html</link>
	            <description><![CDATA[
	            	            Since Apple OS X is built atop BSD Unix (its lineage goes back to NeXT, whose acquisition by Apple brought Steve Jobs back to Apple), I'm surprised that we don't see more experimental ports of popular EDA tools recompiled for this platform.

Of course, I don't know the porting requirements, they are probably non-trivial since OpenOffice for the Mac is available as a separate product called NeoOffice (usually lagging by a few weeks).  But things should work at the platform-independent level, such as Eclipse with Java-based plug-ins.  (I know from past experiments with Platform Express on my old eMac!)	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 20 May 2010 01:14:14 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2708-597</guid>
	            <title><![CDATA[Eeeek! Cadence is going to acquire Denali: Make Mine A Double]]></title>
	            <link>/201005132708/myblog/blog/z000c-eeeek-cadence-is-going-to-acquire-denali.html</link>
	            <description><![CDATA[
	            	            Tonight we're gonna party like is 3609!

https://www.denali.com/en/events/register/denali_dac_party.jsp	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 19 May 2010 18:44:43 -0500</pubDate>
            </item>
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                <guid isPermaLink="false">2713-596</guid>
	            <title><![CDATA[Problems testing your circuit board/system? Kozio has the answer!: Kozio is the solution ]]></title>
	            <link>/201005142713/myblog/blog/z0022-problems-testing-your-circuit-boardsystem-kozio-has-the-answer.html</link>
	            <description><![CDATA[
	            	            Airvana has been using Kozio Diagnostics for 3+ years now for DVT and post-production testing in our Femtocells.  Kozio was a life saver for us, since we were swamped with other projects and unable to hire anyone in time to write tests for this new project.  Within 4 weeks, Kozio was able to give us a working POST and Diagnostic (offline standalone diags) just from a schematic and block diagram.  

We also used Kozio's kDevelopment kit.  From which we were able to write our own 'tests & utilities' for our ever evolving Radio section and have these tests running alongside Kozio's tests.  

Another plus was their simple scripting language, this allowed our manufacturing team to quickly write their own 'test scripts' to use in post-production.

As stated in other posts here, Kozio was able to get back with solutions to almost any problem/request within a day.  The engineers were always professional and knowledgeable.  

 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 19 May 2010 16:56:01 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2713-595</guid>
	            <title><![CDATA[Problems testing your circuit board/system? Kozio has the answer!: Kozio really is the best diagnostic on the market]]></title>
	            <link>/201005142713/myblog/blog/z0022-problems-testing-your-circuit-boardsystem-kozio-has-the-answer.html</link>
	            <description><![CDATA[
	            	            ADI Engineering has relied on Kozio's Diagnostic Tools to design verification test and manufacture test over 30 designs in the last 6+ years.  I cannot agree more with Clive about the ease of working with the Kozio design team.  Send them a block diagram and receive a full blown, customized diagnostic package in no time that actually works out of the box.  Upgrade a component, make a board mod, tweak an interrupt assignment, and get a diagnostic update in hours.  And when there are hardware problems, the tools will pinpoint the problem for you.  Really takes the guesswork out of board debug.  We've fully validated boards in one afternoon using Kozio's tools.  These guys are absolute miracle workers. Too good to be true?  I say, "Too good not to use them".	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 18 May 2010 21:32:48 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2603-594</guid>
	            <title><![CDATA[Video: FREE SmartFusion Mixed-Signal FPGA Eval Kit: Eval Kit live in action ]]></title>
	            <link>/201004222603/myblog/blog/z0002-video-free-smartfusion-mixed-signal-fpga-eval-kit.html</link>
	            <description><![CDATA[
	            	            To help spark some ideas on using this kit, there is a video of our demo design posted on the actel site.
http://www.actel.com/FPGA/SmartFusion/video/evalkit.html
This uses the Hyperterminal, Ethernet, Analog, I2C, UART and OLED drivers. 
All source files are also posted on the web page for you to use an play with. 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 17 May 2010 21:50:39 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2704-593</guid>
	            <title><![CDATA[People Problems: Complacency.]]></title>
	            <link>/201005122704/myblog/blog/z0019-people-problems.html</link>
	            <description><![CDATA[
	            	            Because 1.  We've always done it that way. 
        2.  It's never happened before. 
        3.  I never knew that meant catastrophic failure could happen. 
        4.  I didn't know how important it was. 
        5.  I didn't get training. 
etc. etc.  The list can go on and on.  Suffice it to say the military aviation world has the same issues, and yet they still have incidents.  The biggest factor is Complacency Kills.  When we see something that is normally an issue, it causes the hackles to raise on the back of our neck.  We know to act.  The problem is we become accustomed to the situation and we forget to pay attention to those same warnings. This is how human error mishaps occur.  	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 17 May 2010 13:15:33 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2713-592</guid>
	            <title><![CDATA[Problems testing your circuit board/system? Kozio has the answer!: Enveloped in Very Cool Technology]]></title>
	            <link>/201005142713/myblog/blog/z0022-problems-testing-your-circuit-boardsystem-kozio-has-the-answer.html</link>
	            <description><![CDATA[
	            	            Max –

It was a pleasure meting up with you in San Jose and I look forward to many more conversations. 

Although “testing” is not glamorous, we continue to see amazing new and cool technology and that, along with happy customers, makes our business very enjoyable. We are in a unique industry position where we see and learn from hundreds of designs, and then encapsulate that experience in a standard product along with support and services. Our engineering staff is amazing at delivering embedded software for customer designs even though we rarely see the actual hardware. And yet, they have an extremely high success rate of running our software on bare hardware on the first attempt. And better yet, they do a great job of troubleshooting based on working with hundreds of designs and varying technologies. Our team adds value to our customer’s team both in hardware and embedded software knowledge, reducing the risk of getting all this very cool technology to market.

Your writing style is very enjoyable and noted as I embark on my own blogging.

Thank you, 
Joe @ Kozio
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sat, 15 May 2010 15:29:48 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2682-591</guid>
	            <title><![CDATA[Avatech: The PCB Designer (needs a name): Name the Circuit Board Designer]]></title>
	            <link>/201005072682/myblog/blog/z0022-avatech-the-pcb-designer-needs-a-name.html</link>
	            <description><![CDATA[
	            	            Ed "Off-Grid" Gerouter	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 14 May 2010 22:07:51 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2713-590</guid>
	            <title><![CDATA[Problems testing your circuit board/system? Kozio has the answer!: What fun is that?]]></title>
	            <link>/201005142713/myblog/blog/z0022-problems-testing-your-circuit-boardsystem-kozio-has-the-answer.html</link>
	            <description><![CDATA[
	            	            You mean that the board bring-up method would be to run this to verify the hardware first?  Instead of just trying to boot the OS (and/or the app) and then pulling on strings until all HW and SW issues are found?  What fun is that?  8^}

Disclaimer:  I know these guys. Good stuff!
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 14 May 2010 21:16:37 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2688-589</guid>
	            <title><![CDATA[You’re only as fast as your slowest communications: One more Comment]]></title>
	            <link>/201005102688/myblog/blog/z000e-youre-only-as-fast-as-your-slowest-communications.html</link>
	            <description><![CDATA[
	            	            Brian,

I forgot to mention the most important criteria. The performance of 15-25 fps of SDV and 5-10 fps of HDV is achieved in "transaction-based-co-emulation" with our video transactors, not in "in-circuit-emulation".

Ancora saluti,
lauro	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 11 May 2010 21:41:29 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2688-588</guid>
	            <title><![CDATA[You’re only as fast as your slowest communications: A comment]]></title>
	            <link>/201005102688/myblog/blog/z000e-youre-only-as-fast-as-your-slowest-communications.html</link>
	            <description><![CDATA[
	            	            Ciao Brian,

you wrote "including those claiming higher raw emulation speed", which I presume means ZeBu from EVE.

You also wrote: "transforming a five hour video frame simulation into a 30 second run on the Veloce platform." I assume you mean “one frame per 30 seconds”.

So, let's straighten this out. ZeBu processes a standard video steam between 15 and 25 frames–per-second and a high-definition video steam between 5 and 10 frames-per-second.

You are welcome to come by and see for yourself or you can talk to our users in the video business.

Saluti,
lauro
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 11 May 2010 21:32:20 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2682-587</guid>
	            <title><![CDATA[Avatech: The PCB Designer (needs a name): Being Older....]]></title>
	            <link>/201005072682/myblog/blog/z0022-avatech-the-pcb-designer-needs-a-name.html</link>
	            <description><![CDATA[
	            	            He might be a "Phil", but definitely not a "Matt". 
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 11 May 2010 11:52:58 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2682-586</guid>
	            <title><![CDATA[Avatech: The PCB Designer (needs a name): Name that PCB Engineer]]></title>
	            <link>/201005072682/myblog/blog/z0022-avatech-the-pcb-designer-needs-a-name.html</link>
	            <description><![CDATA[
	            	            He looks like a Henry to me.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 10 May 2010 12:56:28 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2680-585</guid>
	            <title><![CDATA[EVs may offer only bland driving: Re: What was Robertson thinking???]]></title>
	            <link>/201005062680/myblog/blog/z0000-evs-may-offer-only-bland-driving.html</link>
	            <description><![CDATA[
	            	            Lee, people buy top-end cars for reasons beyond performance.  Namely, they want to own something that displays gems of mechanical engineering, that produces mechanical musical to hear, and delivers a sensory experience when driving.  Robertson is dead on: no marketing guru is going to be able to conceal the soulless look of battery packs and the golf-cart soundtrack and power delivery of an electric vehicle.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sat, 08 May 2010 18:13:12 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2654-584</guid>
	            <title><![CDATA[New debug capabilities from Mentor, ARM and Lauterbach: Why Stop at Mass Production?]]></title>
	            <link>/201005032654/myblog/blog/z000e-new-debug-capabilities-from-mentor-arm-and-lauterbach.html</link>
	            <description><![CDATA[
	            	            A feature of the TMC is that it enables its tracing capabilities "right up to the point of mass production." Why stop there? Why not leave it on in customer-shipped products? I say, leave it on forever!

Airlines have been doing this for years. Cars are doing it more and more. It's called a "black box" and is used to diagnose crashes. Microsoft does this, "The application, goofy.exe, crashed. Click here to send dump data to Microsoft." I've used this feature in the past for consumer electronic products that I have worked on.

Can TMC be used in customer-shipped products?	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sat, 08 May 2010 05:28:40 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2680-583</guid>
	            <title><![CDATA[EVs may offer only bland driving: What was Robertson thinking???]]></title>
	            <link>/201005062680/myblog/blog/z0000-evs-may-offer-only-bland-driving.html</link>
	            <description><![CDATA[
	            	            Robertson may be right that there are not many differentiators for electric propulsion systems today but I think that all we have to do is give the marketing geniuses a little time. If they were able to make cigarettes sexy, they will have a field day with EVs. But the thing that really puzzles me is why the CTO of an EV components company would shoot himself in the foot by knocking his own technology. 

It's tough to say what might have motivated such a highly-placed executive to imply that the electric propulsion technology that lies at the heart of his business is generic and difficult to market but one could speculate that: 

1 - He's been living on Mars and has not heard about the huge oil spill in the Gulf Coast.
2 - He's never driven a Tesla Roadster
3 - He's got some very interesting EV propulsion technology he's about to announce that will provide some very dramatic differentiation from the systems commonly used in today's vehicles. 

After covering the hi-jinks of Silicon Valley execs for close to two decades, I'll go with door #3.

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 07 May 2010 15:25:42 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2642-582</guid>
	            <title><![CDATA[Cadence outlines vision with EDA360: Think Different?]]></title>
	            <link>/201004292642/myblog/blog/z000d-cadence-outlines-vision-with-eda360.html</link>
	            <description><![CDATA[
	            	            Thanks, Brian!  "Personally, I believe that the role of ESL is more important than this paragraph states ..." and I thought it was just me!  You would think that ESL would be the pivot point in figuring out your system, its requirements satisfied by the software 'app(s)' paired with the particular hardware it would run on.  Maybe Cadence wanted to constrain this due to their lack (to my knowledge) of their own ESL design platform a la Mentor's Vista or Synopsys (CoWare, Innovator).  [No, my speculation that they would buy SoC Designer from Carbon has not come to pass ... yet!]  Constrain the problem to what is available at present from, say, OVP World (n.b., which Cadence participates in!).

Last night, after watching Jon Stewart beat up Steve Jobs and Apple on The Daily Show, I revisited EDA360 and it occurred to me that while Cadence's EDA360 didn't contain anything new, it was akin to Apple's past campaign: Think Different.  And at least one Cadence presenter appeared wearing a black turtleneck! :)

http://tech.fortune.cnn.com/2010/04/29/jon-stewart-to-steve-jobs-chill-baby/
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 29 Apr 2010 22:28:29 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2520-581</guid>
	            <title><![CDATA[Network Neutrality Struck Down: Next stop: The Department of Commerce]]></title>
	            <link>/201004062520/myblog/blog/z000a-network-neutrality-struck-down.html</link>
	            <description><![CDATA[
	            	            This was a strange case from its origins, given the extent to which, for decades, the FCC acted like they were in the pocket of the cable companies. Now that they have been deemed entirely irrelevant by the US Court of Appeals, one wonders if non-technical aspects of communication policy will fall to the Department of Commerce. One also wonders if that organization is in any way prepared to regulate carrier behavior.

I don't think this marks a death knell for network neutrality but it does deal it a severe blow. Meanwhile, the Court of Appeals has again grabbed its favorite tool - the can opener - and pried the lid off another can of worms.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 29 Apr 2010 21:54:46 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2638-580</guid>
	            <title><![CDATA[Xilinx unveils new class of device – an Extensible Processing Platform: Between FPGA and Platform ASIC]]></title>
	            <link>/201004272638/myblog/blog/z0002-xilinx-unveils-new-class-of-device-an-extensible-processing-platform.html</link>
	            <description><![CDATA[
	            	            Max, my impression from your report and what was just released on the EE Times strikes me as an approach between that of FPGA (with onboard processors) and what was (once?) called Platform ASIC (LSI, Toshiba - with online search you might still find collateral on LSI's former RapidChip product).  The Platform ASIC was envisioned as being halfway from FPGA to custom ASIC ... 

So the embedded hard IP is a base SoC, not just a CPU as in the Xilinx Virtex, with the rest programmable a la FPGA.  Cool!	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 28 Apr 2010 00:27:15 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2627-579</guid>
	            <title><![CDATA[Cadence announces verification computing platform: Everything and the Kitchen Sink]]></title>
	            <link>/201004262627/myblog/blog/z000e-cadence-announces-verification-computing-platform.html</link>
	            <description><![CDATA[
	            	            Since Cadence wasn't giving out further details, Brian, that leaves the rest open to wild speculation! :)

But seriously, there may be important competitive information that they're holding back, maybe until later.  For one, is the test bench being accelerated along with the DUT on this machine?  Should this be an advance, given that test benches are not usually written with synthesis in mind, nevermind emulator compatibility rules.  Is their emulation mapping so advanced that such constraints are removed?  And can these be high level test benches in SV or SystemC (say, for OVM), even?  A 'yes' to any of these, maybe they're holding back for DAC ...

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 26 Apr 2010 23:28:04 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2619-577</guid>
	            <title><![CDATA[Amazing Beans: Video of mandatory exercise program for sedentary engineers: Techbites uniforms]]></title>
	            <link>/201004232619/myblog/blog/z000c-amazing-beans-video-of-mandatory-exercise-program-for-sedentary-engineers.html</link>
	            <description><![CDATA[
	            	            I am only going to do it if I get one of those new techbites uniforms :)	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 23 Apr 2010 16:14:15 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2597-576</guid>
	            <title><![CDATA[Synopsys, Actel press release fails to deliver: Standard FPGA synthesis tool press release]]></title>
	            <link>/201004212597/myblog/blog/z000d-synopsys-actel-press-release-fails-to-deliver.html</link>
	            <description><![CDATA[
	            	            With Synplify Pro AE being a standard part of the Actel flow, if there was any news here, it was that this release didn't come out till six weeks after the SmartFusion announcement. 

A synthesis tool that deals with digital logic as well as analog? That would be news and would certainly merit more than a standard synthesis tool press release. 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 23 Apr 2010 03:00:57 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2587-575</guid>
	            <title><![CDATA[Fluffy Spider Technologies (FST) to demo at ESC: Skinput]]></title>
	            <link>/201004192587/myblog/blog/z000c-fluffy-spider-technologies-fst-to-demo-at-esc.html</link>
	            <description><![CDATA[
	            	            I think I are watching too many supernatural movies, because today I swore I saw an advertisement for Skinput. Just what is Skinput? It is a prototype touch display that shoots an image to your skin and you use your arm and hand like a keyboard. So instead of pulling out your cell phone to send that next text message you would pull up your sleeve and shoot a picture of a keyboard onto your arm. From there the vibrations would be sensed and precisely what you are trying to type (on your arm) would be sent! If this sounds like something from Back to the Future it is because it is! This technology is not ready for use yet but could be as early as two years from now.
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 20 Apr 2010 04:59:23 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2582-574</guid>
	            <title><![CDATA[Writing 4 Engineers: Grammar and punctuation in general: and don't forget the perils of spelling checkers]]></title>
	            <link>/201004192582/myblog/blog/z0002-writing-4-engineers-grammar-and-punctuation-in-general.html</link>
	            <description><![CDATA[
	            	            one shouldn't ignore the profound confusion that arises from the inappropriate use of spelling checkers. Wonderful invention, but generally not able to let you know you have used a totally inappropriate word, perfectly spelled. 

As an example, I grimace whenever I see a business card listing a job title "Principle Engineer" vs. "Principal Engineer". Perfectly spelled, but really not the right word. While I could, maybe,  argue for the former, I certainly hold the later is the more appropriate usage. 

There again, I'm just one of John Cooley's "marketing-droids". What do I know.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 19 Apr 2010 19:44:59 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2565-573</guid>
	            <title><![CDATA[Sound design needed: how practical]]></title>
	            <link>/201004162565/myblog/blog/z0000-sound-design-needed.html</link>
	            <description><![CDATA[
	            	            Really?  Gee I can make my VW sound like a Harley now (which is a trademarked sound).  Why don't they figure out how to chase the deer off the dark highways and put that on all cars?  That's a far more dangerous and likely encounter.  I don't think those little "deer whistles" work.  

We're really great about thinking of how we can fix something that we just fixed.  Problem: cars are noisy.  Fix: make them quieter.  Problem: cars are too quiet.  Fix: fake some noise.  

You know decades ago, we were going to silence cars by neutralizing the sound of car engines electronically (DSP sound cancellation) so that mufflers wouldn't cause the undesired backpressure on the cylinders, and otherwise so we could hear our nice stereos in the car without outside road and traffic noise.  But generally, that never happened, even though it was technically quite feasible.  

Many decades ago, when Ma Bell (the real one) was upgrading its toll switches to electronics, they found that great numbers of people were hanging up the phone before their long distance (remember that term?) call was connected.  They found that the new switches were so quiet that without the clicking in the phone that people were so used to from the relays/crossbars connecting, the caller assumed the call was gone afoul and would just hang up.  The phone company had to insert random noises and clicks into the line so the caller felt like they were "being connected."  It worked. People now believed the eqpt hadn’t abandoned them.

How to benefit far more people?  Put similar noise-canceling systems on major highways and along neighborhoods so people don’t hear the drone of constant traffic.  Clearly, today’s “sound barriers” don’t work. 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 16 Apr 2010 23:34:03 -0500</pubDate>
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                <guid isPermaLink="false">2266-572</guid>
	            <title><![CDATA[Hurray – ESC India 2010 here I come!: Welcome to Bangalore]]></title>
	            <link>/201003052266/myblog/blog/z0022-hurray-esc-india-2010-here-i-come.html</link>
	            <description><![CDATA[
	            	            Hi Clive,
  Hope you have a great time in Bangalore :). Other places to visit:
Bull temple, ISKCON temple
  If you have time, visit Hampi (226 miles from Bangalore) famed for its magnifi
cent 14th century architecture and sculptures.

 Cheers,
 Ram
PS: I am guessing you watched Slumdog Millionaire..
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 15 Apr 2010 17:57:31 -0500</pubDate>
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                <guid isPermaLink="false">2558-570</guid>
	            <title><![CDATA[Review: New on-line filter design tool yields quick first-cut results: Comments on the filter tool design considerations by the author]]></title>
	            <link>/201004142558/myblog/blog/z0028-review-new-on-line-filter-design-tool-yields-quick-first-cut-results.html</link>
	            <description><![CDATA[
	            	            Dear Joshua, 

It is nice to have such an obviously experienced user take this for a trial run as having only internal folks looking at it thus far, we will always miss some things. We will pursue some of your ease of use comments as we accumulate those from other users as well, but let me comment a bit on some of the design strategy type things you pointed out. 

The semi-automatic flow was structured to increase the chance of a successful design for novice users. As time went by, I sort of craved the chance to push the limits and we added the manual design flow where it is actually quite easy to get error messages that the requirements exceed the available op amps (something we also need work on, but that is a different issue). Since I wanted to support a single stage design up through 20MHz in this flow, a gain of 10 in that single stage starts to ask for some pretty high bandwidth devices in the algorithms I developed. So we capped it at 10, but moved the higher gain flexibility into the manual option. Kind of wanted to minimize the chance for error messages in this “novice designer” flow. 

The pole and gain sequencing was actually kind of interesting for me to encode. I don’t think the work that is out there on this topic has really considered all the tradeoffs associated with this issue. As a starting point, I developed some approximate minimum bandwidth equations for each topology where I was trying to hold enough amplifier bandwidth margin (to the target poles) to keep less than 2% stage shape variation for a +/-15% amplifier bandwidth or gain bandwidth variation. Once I had that working, I started experimenting with different gain and pole segmentation strategies. Essentially, as the gain and Q go up for stage, the required amplifier bandwidth increases very fast. One goal I had was bias the semi-automatic design flow to give some chance to using the same op amp in every stage. I noticed in those vendor tools, that do offer up a required amplifier bandwidth estimate, a wide spread in those requirements with some of the other strategies – sometimes > 100:1. What I found, was that if I sequence the gains from low to high while also sequencing the required Q’s from high to low (in going from input to output), I got a better clustering for required amplifier Bandwidths and therefore a better chance of being able to do the design with the same part – where that part is not just massive overkill speed wise as you see in some of the tools. 

Now I know there is a bias towards putting all the gain up front for “spot” noise reasons. However, with the strategy we implemented here, I didn’t want much gain in the highest Q first stage but I did want the lower Q poles and more gain towards the end of multi-stage designs. Doing that, we get considerable lower “integrated noise” I don’t have the horsepower to try to write an optimization routine for this, but if you look at Appendix 3 in the users guide we tried to illustrate this where it is pretty easy to see that the higher Q stages always produce a high noise peak in and of themselves – if these are towards the end of the filter chain you get this peaked broadband noise that will integrate to a higher RMS noise than what we get with the strategy we used. Another issue that our segmentation strategy helps is the buildup of overshoot issues going through a filter. One thing often missed is that it is actually pretty easy to clip the output or input in a multi-stage filter design. In filters with >1 gain, putting most of the overshoot first (with the highest Q stage operating at low gains) and then essentially rolling off that overshoot in the later stages seems to help this. 

Again, I am very far from claiming what we have here is “optimum” but it seems to achieve a nice compromise for the issues I mentioned here. 

That was the main issue you noticed and I was expecting some consternation on the choices we made. 

On some of your other comments, 

One option to try other gain and Q sequencing is to let the semi-automatic flow do its thing, then use the manual flow to adjust that to what you might believe would work better. 

Your comment on the max. gain of 5 in a manual design flow, where you expected a gain of 10. I suspect this is where you had done a 3 stage (5th order) design then jumped back to the beginning to try a manual design. It probably thought you were still doing a 3 stage design where it does limit to a gain of 5 maximum in each stage. I did try this, jumping back to the Requirements page after doing a 5th order design, you have to be careful to change the order to 4 when you switch to manual entry. 


Michael Steffes, iSim Active Filter Design team lead. 






	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 14 Apr 2010 21:27:48 -0500</pubDate>
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                <guid isPermaLink="false">2545-567</guid>
	            <title><![CDATA[You have to innovate in areas that really matter: Two steps forward, one step back]]></title>
	            <link>/201004122545/myblog/blog/z000e-you-have-to-innovate-in-areas-that-really-matter.html</link>
	            <description><![CDATA[
	            	            Brian, I responded to the EE Times version of this article.  My concern is that the speed of innovation has slowed because of capital issues, throttling the start-ups on which so much EDA innovation relies upon and leaving the major EDA firms shoring up and incrementally improving their existing tool offerings.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 12 Apr 2010 18:26:13 -0500</pubDate>
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                <guid isPermaLink="false">2519-566</guid>
	            <title><![CDATA[Cool Beans: Now that's what I call customer service!: Terri Pratchett fan, aren't you?]]></title>
	            <link>/201004062519/myblog/blog/z000c-cool-beans-now-thats-what-i-call-customer-service.html</link>
	            <description><![CDATA[
	            	            "quaffing is like regular drinking, except you tend to spill more down your chest"

Little give-away that you are reading too much discworld novels :-))

Maybe we should add a column for exchange on the discworld resemblances of some real world aspects.

Besides Doug Adams, Terri is another author any engineer should read, IMHO.



Thomas	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 12 Apr 2010 15:21:27 -0500</pubDate>
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                <guid isPermaLink="false">2531-565</guid>
	            <title><![CDATA[Cadence and Virage put out obfuscated message for their seminar: U R so right!]]></title>
	            <link>/201004072531/myblog/blog/z0000-cadence-and-virage-put-out-obfuscated-message-for-their-seminar.html</link>
	            <description><![CDATA[
	            	            Hi Brian -- my name is Susan Peterson, and I am Director of Verification IP Product Management for Cadence Design.  As such, I am responsible for the offending invitation -- we are so busted!  I agree with your assessment -- we get so used to throwing around acronyms that we forget to speak plain English. I especially appreciate that you took the time not just to criticize, but to recommend an alternative -- which we will incorporate into our next round of invitations.  Thanks for the reminder...	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 07 Apr 2010 21:55:57 -0500</pubDate>
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                <guid isPermaLink="false">2506-563</guid>
	            <title><![CDATA[Reason #4 to Customize a Processor Core - Use an Automated Process: The best is not alweays the best]]></title>
	            <link>/201004052506/myblog/blog/z000c-reason-4-to-customize-a-processor-core-use-an-automated-process.html</link>
	            <description><![CDATA[
	            	            I would be more inclined to defend Paula's article. While it may be true that the very smallest or fastest implementation may come from a dedicated solution, these tend to be fixed in function, whereas in many cases there is a need for both performance, time to market and flexibility. Consider an audio codec. I am sure you could build an MP3 decoder in hardware much smaller and faster than a Tensilica processor, but what happens when the codec is updated, or an additional format is required. With a custom solution you are likely fried unless of course you designed a flexible process to do it - in which case you probably would do no better than their solution. Solutions are all trade-offs between many functions and factors and if there were one right solution, then we would all be out of jobs very quickly.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 06 Apr 2010 16:35:38 -0500</pubDate>
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                <guid isPermaLink="false">2512-562</guid>
	            <title><![CDATA[Gentlemen, start your pens: 42nd North American Power Symposium calls for papers: Metaphor]]></title>
	            <link>/201004062512/myblog/blog/z0028-gentlemen-start-your-pens-42nd-north-american-power-symposium-calls-for-papers.html</link>
	            <description><![CDATA[
	            	            I thoroughly appreciate the metaphor. But, on behalf of all the female engineers, scientists, and writers out there, I need to record an "ouch."	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 06 Apr 2010 15:29:58 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2506-561</guid>
	            <title><![CDATA[Reason #4 to Customize a Processor Core - Use an Automated Process: Lesson from VLSI - learned or not?]]></title>
	            <link>/201004052506/myblog/blog/z000c-reason-4-to-customize-a-processor-core-use-an-automated-process.html</link>
	            <description><![CDATA[
	            	            Back-end or VLSI Designers know that critical parts of hardware need to be designed out manually. Its known as 'custom layout', as opposed to 'cell/library based layout'. Can configured processors, such as those of Tensilica be used to create critical applications, where speed is more important than time-to-market?
   However, other (non-sensitive) applications would, in most cases,  be better served if a configured processor is used.
   Any ideas on improving both time-to-market and speed simultaneously?
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 06 Apr 2010 14:54:06 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2421-560</guid>
	            <title><![CDATA[ITRS Roadmap and Formal Verification: Jasper Design: ITS Roadmap and formal - spreading the technology via classes]]></title>
	            <link>/201003252421/myblog/blog/z000e-itrs-roadmap-and-formal-verification-jasper-design.html</link>
	            <description><![CDATA[
	            	            Hi Holly,
The ITRS roadmap is interesting and the importance of formal verification as a design productivity enhancing technology is a hope and promise that can be fulfilled.  Even then, when I work in verification in the chip industry, I do not see the momentum picking up in this direction as much as its promise.

Formal has a lot of promise and it can become a block level verification technology.  With SystemVerilog, and OVM/VMM/UVM there is a direction in which engineers are writing classes with constraints for constrained random testing.  In this methodology, there is no participation from formal verification vendors.  If we come out with classes that are reusable and are formal compliant, it will enable spreading this technology to the mainstream RTL design and verification engineers.
Vivek
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 02 Apr 2010 17:39:04 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2488-558</guid>
	            <title><![CDATA[TechBites Unvells Eco-Friendly  Print Edition as Part of a Global Carbon Sequestration Initiative: Nice....]]></title>
	            <link>/201004012488/myblog/blog/z001d-techbites-unvells-eco-friendly-new-print-edition-part-of-a-global-carbon-sequestration-initiative.html</link>
	            <description><![CDATA[
	            	            I have shelves and shelves of old magazines and way out of date databooks in my home office. I can see adding these issues to the collection (if I can find room).

Thanks for the random Yugo comment as I have not heard a good one in years.  I have since burned all pictures or documents that can prove that I once owned one of these.

Gene	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 01 Apr 2010 18:51:22 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2448-557</guid>
	            <title><![CDATA[Has there really been no progress in analog?: There is some interesting stuff going on]]></title>
	            <link>/201003292448/myblog/blog/z000e-has-there-really-been-no-progress-in-analog.html</link>
	            <description><![CDATA[
	            	            Hi Brian -- I know what you mean, but there is some interesting stuff going on. The folks at Ciranova are doing some amazing work with a tool that automates analog cell placement (they use Genetic Algorithms to generate multiple solutions in a very short time). Also the guys and gals at Tanner EDA have some very cool technology. If you get the time you should chat with both of them (call me if you need contacts) -- cheers -- Max 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 31 Mar 2010 21:25:59 -0500</pubDate>
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                <guid isPermaLink="false">2449-556</guid>
	            <title><![CDATA[Cool Beans: Yet another mind-boggling video!: Awesome!]]></title>
	            <link>/201003292449/myblog/blog/z000c-cool-beans-yet-another-mind-boggling-video.html</link>
	            <description><![CDATA[
	            	            Oh man, it's such a cliche, I know, but I can't resist this creative stuff. Awesome!	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 30 Mar 2010 02:05:48 -0500</pubDate>
            </item>
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                <guid isPermaLink="false">2448-555</guid>
	            <title><![CDATA[Has there really been no progress in analog?: Analog is the Real World]]></title>
	            <link>/201003292448/myblog/blog/z000e-has-there-really-been-no-progress-in-analog.html</link>
	            <description><![CDATA[
	            	            Hi, Brian!

I had the same thoughts recently when I came across Agilent's EEsof web site and noticed that not much as changed in a decade ... Improved?  Yes!  New?  Uh, not much ...

Sure, there is now 'ESL' but that seems to be C++ models of analog components.

The problem in dealing with analog or AMS design is that the outlook is a bit different from the digital hardware and/or software perspective.  Four points that come to mind: continuous time, frequency domain, physics, network analysis.  It has been a tremendous effort (lots of cross-education) to square analog continuous time with digital discrete time perspectives in VHDL-AMS and Verilog-A/AMS.

What's funny is that there was a recent unscientific survey on VHDL-AMS issues to be tackled next.  It was open so I sent in my vote to Ernst Christen ... for me, #1 was mixed netlists, #2 was frequency domain.  Omigosh ... it has been a decade since I had submitted a brief on behalf of my former Chicago-area major telecoms employer on the need for frequency domain support in VHDL-AMS to make it useful for RF designers!

This isn't meant to be a slam on the 1076.1 committee's work, I appreciate how much work it has taken to get workable baseband AMS designs in EDA.  And then the back and forth to resolve it with mainline digital VHDL and Verilog.  But my impression, with many years away from that effort, is that the focus has been on design and not on verification.  Because the analog pieces are created and verified by other means (and prototyping, including building of isolation chambers, etc.), my impression is that the analog parts are 'known good' and the focus in AMS is on the baseband interaction.  In other words, like the early days of IP reuse and verification in the digital domain ("Huh?  The block works in its test bench ... why not in the system?').

gld
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 30 Mar 2010 00:50:49 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2442-554</guid>
	            <title><![CDATA[The cost of IP integration is rising dramatically: What Integration Ready IP Means to Me]]></title>
	            <link>/201003292442/myblog/blog/z0030-the-cost-of-ip-integration-is-rising-dramatically.html</link>
	            <description><![CDATA[
	            	            Hi, Dave!

From my own past experience, I would say ... the more work that I have to do in order to understand and use an IP, the less ready it is for integration! :)

But seriously, the key is providing sufficient information to the design team in order to connect and 'integrate' an IP into the design, whether TLM or RTL (or both).  That can be done in either manual or automation-assisted processes, the key is to have the information ready and accessible.  For an example of automation, the two of us know that design environments (DE's) supporting IP-XACT (IEEE 1685) such as from Duolog, Magillem, Mentor Graphics, Synopsys and Cadence (among others) can extract that information and use it for design flows that they support.

Even in a manual process, having that information is helpful to productivity.  Automating it enhances your return manyfold!

gld
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 29 Mar 2010 23:38:40 -0500</pubDate>
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                <guid isPermaLink="false">2440-553</guid>
	            <title><![CDATA[Must read for Hardware Designers/Managers Considering C/C++ Synthesis: re: Not always the best]]></title>
	            <link>/201003292440/myblog/blog/z000d-must-read-for-hardware-designersmanagers-considering-cc-synthesis.html</link>
	            <description><![CDATA[
	            	            Brian,

Of course, marketing and politics often win the game ASSUMING that a solution fundamentally meets a minimum need.  And, for abstract modeling and simulation-only test benches, C/C++/SystemC certainly more than just meet the basic needs.  But for hardware design (synthesis), Brian?  Really?  Most hardware engineers I meet would seriously question that for more than niche applications – and, I’m guessing that it’s going to take more than politics and marketing to overcome their objections.

By your argument, I'd think that it would even be more likely that C/C++ would be the languages of choice for SOFTWARE engineers developing parallel software applications.  Most of them already use C-based languages, so they'd be even better candidates than hardware designers.  But, how many of them are counting on automatic parallelization (the same basic technology that powers behavioral synthesis tools) for their solutions to multi-threading/multi-core/parallel computation?  Few do because it doesn’t meet their minimum needs (because of the limitations of automatic parallelization).

Of course, there may come a time when 30-100%+ area/timing/... penalties are acceptable or when design considerations like tight latency guarantees don't matter, but I have my doubts in the general case.  In my experience, most hardware designers care about power, timing, area, etc. and cannot compromise.  (With SystemC, you can express anything and control fine details – but, with synthesis, it’s RTL by another name except for loop-and-array apps.  Sure, some will adopt it, but that’s much different from saying it’ll be a mainstream replacement to RTL).

Until that time, a parallel language will be the only tool that meets the minimum needs of most hardware designers.  (And, SystemC doesn’t offer much over RTL when synthesis is a requirement.)
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 29 Mar 2010 23:05:48 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2440-552</guid>
	            <title><![CDATA[Must read for Hardware Designers/Managers Considering C/C++ Synthesis: Not always the best]]></title>
	            <link>/201003292440/myblog/blog/z000d-must-read-for-hardware-designersmanagers-considering-cc-synthesis.html</link>
	            <description><![CDATA[
	            	            Hi George. I think we all know that if the best technology always won, then the world would be a very different place than it is today. Unfortunately, things like marketing and politics often get to decide the eventual fate of technology.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 29 Mar 2010 13:57:32 -0500</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">2341-551</guid>
	            <title><![CDATA[Survey of the Value of Formal Verification in  Japan: Thanks from Holly]]></title>
	            <link>/201003162341/myblog/blog/z000e-survey-of-the-value-of-formal-verification-in-japan.html</link>
	            <description><![CDATA[
	            	            Thanks for posting, Brian, and for your Japanese readers, see the following link to the article in Nikkei Tech-On...techon.nikkeibp.co.jp 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 26 Mar 2010 19:32:47 -0500</pubDate>
            </item>
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                <guid isPermaLink="false">2435-550</guid>
	            <title><![CDATA[Brian Bailey says adoption of ESL is going just fine.: Helpful review]]></title>
	            <link>/201003262435/myblog/blog/z000d-brian-bailey-says-adoption-of-esl-is-going-just-fine.html</link>
	            <description><![CDATA[
	            	            Good points made here -- citing supporting data would have raised my rating. 	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 26 Mar 2010 17:11:00 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2432-549</guid>
	            <title><![CDATA[Tektronix launches online community for oscilloscope users (free scope): are foreigners allowed?]]></title>
	            <link>/201003252432/myblog/blog/z000c-techtronix-launches-online-community-for-oscilloscope-users-free-scope.html</link>
	            <description><![CDATA[
	            	            are we foreigners with H-P scopes allowed to visit?	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 26 Mar 2010 08:10:15 -0500</pubDate>
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	        	        <item>
                <guid isPermaLink="false">2432-548</guid>
	            <title><![CDATA[Tektronix launches online community for oscilloscope users (free scope): Thanks for your visit - and your write-up!]]></title>
	            <link>/201003252432/myblog/blog/z000c-techtronix-launches-online-community-for-oscilloscope-users-free-scope.html</link>
	            <description><![CDATA[
	            	            Glad you found our new online community (or that we found you via one of our emails!). Oh, if only we could serve beer...

Our goal with Scope Central is to deliver test and measurement information, and be the source of all things oscilloscope-related.  We welcome any suggestions of content, functionality--things that would make you return and visit often.

I appreciate the mention and hope to see you back at Scope Central (where there absolutely is no dress code).

Suzanne, Tektronix
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Thu, 25 Mar 2010 23:05:56 -0500</pubDate>
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                <guid isPermaLink="false">2345-547</guid>
	            <title><![CDATA[Announcing the New Hw/Fw Interface Community: Good stuff!]]></title>
	            <link>/201003172345/myblog/blog/z003d-announcing-the-new-hwfw-interface-community.html</link>
	            <description><![CDATA[
	            	            Sorry I didn't comment on this community previously- but it was St Patricks day in Ireland and I missed a few announcement :)

This is a key emerging area so best of luck with the community. Please keep 'Integration Insights' tagged.

	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 24 Mar 2010 21:21:36 -0500</pubDate>
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