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        <title><![CDATA[TB-Blog - TechBites]]></title>
        <description><![CDATA[TechBites - The Science and Technology Collaborative Community]]></description>
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	            <title><![CDATA[Please help me if you can, Xilinx FIFO Issue!: A Few Comments]]></title>
	            <link>/200912211523/myblog/blog/z0002-please-help-me-if-you-can-xilinx-fifo-issue.html</link>
	            <description><![CDATA[
	            	            FIFOs are always tricky, particularly the asynchronous ones. I believe the Xilinx Async FIFO-16 can only hold 15 values, did you know that?

It might help to understand how they work (and I apologize if you already know all this). The FIFO memory is a block of RAM (either a RAM block or distributed RAM). There are separate read and write counters which point to the different locations (and roll over after terminal count). It's much better to use almost full and almost empty flags to meter the data flow with a little more margin.
Good luck Antti and let us know when you nail the solution.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Mon, 21 Dec 2009 17:23:49 -0600</pubDate>
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