<?xml version="1.0" encoding="UTF-8"?><rss version="2.0">
    <channel>
        <title><![CDATA[TB-Blog - TechBites]]></title>
        <description><![CDATA[TechBites - The Science and Technology Collaborative Community]]></description>
        <link>http://www.techbites.com/</link>
		        	        	        <item>
                <guid isPermaLink="false">1111-220</guid>
	            <title><![CDATA[New eSi-RISC Scalable Soft Processor Cores for ASICs and FPGAs: How much is a "free" processor design worth?]]></title>
	            <link>/200911171111/myblog/blog/z000c-new-esi-risc-scalable-soft-processor-cores-for-asics-and-fpgas.html</link>
	            <description><![CDATA[
	            	            Free, or nearly free, isn't always bad but it also isn't always good.

Antti has aimed us at the real problem for these free cores. Because there is not enough money associated with the design itself, companies don't spend enough to target the core for any particular use. 

A free core without code size optimizations may be fine for a low volume product that doesn't worry about memory cost. For a high volume applicqation code size can easily become a major consideration.

Bottom line is that using a free core may make sense under some circumstances. 

Companies that plan to develop a series of products based on the core should take the time to do a basic financial analysis across multiple projects to determine if the free core is the right call.

Henry	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Wed, 18 Nov 2009 15:55:38 -0600</pubDate>
            </item>
	        	        <item>
                <guid isPermaLink="false">1111-200</guid>
	            <title><![CDATA[New eSi-RISC Scalable Soft Processor Cores for ASICs and FPGAs: 40% is possible, if comparing to NIOS/MicroBlaze]]></title>
	            <link>/200911171111/myblog/blog/z000c-new-esi-risc-scalable-soft-processor-cores-for-asics-and-fpgas.html</link>
	            <description><![CDATA[
	            	            the "Soft-Cores" from leading FPGA vendors are not optimized for code density at all, so 40% saving on code size is sure possible.	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Tue, 17 Nov 2009 18:41:30 -0600</pubDate>
            </item>
	        		    </channel>
</rss>

