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	            <title><![CDATA[Assertions from several points of view: In agreement]]></title>
	            <link>/200912091407/myblog/blog/z000e-assertions-from-several-points-of-view.html</link>
	            <description><![CDATA[
	            	            I fully agree that assertions in a design not only improve productivity, but also provides a greater level of assurance about the design quality and integration of that design in the subsystem.  This is because, as you mentioned, the process of writing assertions causes the team (design and verification) to better understand the requirements.  A misunderstanding of those requirements can quickly be flagged in the review process because SVA is simple enough that the meaning of the requirements is easy to understand. 

Of course, assertions play a big role in the verification of the design during simulation or in formal verification. 
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Ben Cohen (831) 345-1759 
http://www.systemverilog.us/   ben@systemverilog.us 
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Sun, 07 Mar 2010 03:20:00 -0600</pubDate>
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