http://www.techbites.com/ 1587-434 /200912281587/myblog/articles/z000e-esl-verification-languages-what-will-it-be-based-on.html Wed, 06 Jan 2010 20:08:59 -0600 1587-422 /200912281587/myblog/articles/z000e-esl-verification-languages-what-will-it-be-based-on.html 50% of the functionality is now software determined. The problem with this is it's often not exhaustive enough to achieve good coverage of the RTL. It seems to me therefore that the logical conclusion a decade down the road is a combination of a declarative description of the functionality from which the implementation (RTL?) is automatically converted / generated together with an enhanced system-level test derived from models used by software groups. As I've said several times before I feel SystemVerilog is an expensive distraction on a path to solving the real problem. It doesn't have either the declarative nature or the real Object Orientation to handle either of these roles. I do, however, expect the more abstract aspects of SystemC, particularly the TLM spec. to be developed and to achieve the status amongst software & hardware engineers that, say, STL containers have today - SystemC isn't the solution - it's basic building blocks from which application-specific solutions can be built. Finally, from what I've seen, I can't re-implement my transactor tests environments in OVM, and have had a similar amount of trouble with VMM. It seems to me that these only work if you have the same style of application as the model that was in the mind of the authors when they wrote the spec for the library. As such they seem to fit a couple of application areas but don't seem universal enough for a broad range of applications so I predict either a limited life or a major overhaul. ]]> Sat, 02 Jan 2010 10:11:33 -0600