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        <title><![CDATA[TB-Blog - TechBites]]></title>
        <description><![CDATA[TechBites - The Science and Technology Collaborative Community]]></description>
        <link>http://www.techbites.com/</link>
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	            <title><![CDATA[ITRS Roadmap and Formal Verification: Jasper Design: ITS Roadmap and formal - spreading the technology via classes]]></title>
	            <link>/201003252421/myblog/blog/z000e-itrs-roadmap-and-formal-verification-jasper-design.html</link>
	            <description><![CDATA[
	            	            Hi Holly,
The ITRS roadmap is interesting and the importance of formal verification as a design productivity enhancing technology is a hope and promise that can be fulfilled.  Even then, when I work in verification in the chip industry, I do not see the momentum picking up in this direction as much as its promise.

Formal has a lot of promise and it can become a block level verification technology.  With SystemVerilog, and OVM/VMM/UVM there is a direction in which engineers are writing classes with constraints for constrained random testing.  In this methodology, there is no participation from formal verification vendors.  If we come out with classes that are reusable and are formal compliant, it will enable spreading this technology to the mainstream RTL design and verification engineers.
Vivek
	            ]]></description>
                <category><![CDATA[TB-Blog]]></category>
                <pubDate>Fri, 02 Apr 2010 17:39:04 -0500</pubDate>
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